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dmaengine: dw-edma: Create a new dw_edma_core_ops structure to abstract controller operation
The structure dw_edma_core_ops has a set of the pointers abstracting out the DW eDMA vX and DW HDMA Native controllers. And use dw_edma_v0_core_register to set up operation. Signed-off-by: Cai Huoqing <cai.huoqing@linux.dev> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Tested-by: Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230520050854.73160-3-cai.huoqing@linux.dev Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Cai Huoqing
Vinod Koul
parent
487517557f
commit
f9c3403f1f
@ -183,6 +183,7 @@ static void vchan_free_desc(struct virt_dma_desc *vdesc)
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static int dw_edma_start_transfer(struct dw_edma_chan *chan)
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{
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struct dw_edma *dw = chan->dw;
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struct dw_edma_chunk *child;
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struct dw_edma_desc *desc;
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struct virt_dma_desc *vd;
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@ -200,7 +201,7 @@ static int dw_edma_start_transfer(struct dw_edma_chan *chan)
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if (!child)
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return 0;
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dw_edma_v0_core_start(child, !desc->xfer_sz);
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dw_edma_core_start(dw, child, !desc->xfer_sz);
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desc->xfer_sz += child->ll_region.sz;
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dw_edma_free_burst(child);
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list_del(&child->list);
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@ -287,7 +288,7 @@ static int dw_edma_device_terminate_all(struct dma_chan *dchan)
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chan->configured = false;
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} else if (chan->status == EDMA_ST_IDLE) {
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chan->configured = false;
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} else if (dw_edma_v0_core_ch_status(chan) == DMA_COMPLETE) {
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} else if (dw_edma_core_ch_status(chan) == DMA_COMPLETE) {
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/*
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* The channel is in a false BUSY state, probably didn't
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* receive or lost an interrupt
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@ -599,8 +600,6 @@ static void dw_edma_done_interrupt(struct dw_edma_chan *chan)
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struct virt_dma_desc *vd;
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unsigned long flags;
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dw_edma_v0_core_clear_done_int(chan);
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spin_lock_irqsave(&chan->vc.lock, flags);
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vd = vchan_next_desc(&chan->vc);
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if (vd) {
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@ -641,8 +640,6 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
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struct virt_dma_desc *vd;
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unsigned long flags;
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dw_edma_v0_core_clear_abort_int(chan);
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spin_lock_irqsave(&chan->vc.lock, flags);
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vd = vchan_next_desc(&chan->vc);
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if (vd) {
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@ -654,63 +651,32 @@ static void dw_edma_abort_interrupt(struct dw_edma_chan *chan)
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chan->status = EDMA_ST_IDLE;
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}
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static irqreturn_t dw_edma_interrupt(int irq, void *data, bool write)
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{
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struct dw_edma_irq *dw_irq = data;
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struct dw_edma *dw = dw_irq->dw;
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unsigned long total, pos, val;
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unsigned long off;
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u32 mask;
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if (write) {
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total = dw->wr_ch_cnt;
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off = 0;
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mask = dw_irq->wr_mask;
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} else {
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total = dw->rd_ch_cnt;
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off = dw->wr_ch_cnt;
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mask = dw_irq->rd_mask;
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}
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val = dw_edma_v0_core_status_done_int(dw, write ?
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EDMA_DIR_WRITE :
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EDMA_DIR_READ);
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val &= mask;
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for_each_set_bit(pos, &val, total) {
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struct dw_edma_chan *chan = &dw->chan[pos + off];
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dw_edma_done_interrupt(chan);
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}
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val = dw_edma_v0_core_status_abort_int(dw, write ?
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EDMA_DIR_WRITE :
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EDMA_DIR_READ);
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val &= mask;
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for_each_set_bit(pos, &val, total) {
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struct dw_edma_chan *chan = &dw->chan[pos + off];
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dw_edma_abort_interrupt(chan);
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}
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return IRQ_HANDLED;
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}
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static inline irqreturn_t dw_edma_interrupt_write(int irq, void *data)
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{
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return dw_edma_interrupt(irq, data, true);
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struct dw_edma_irq *dw_irq = data;
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return dw_edma_core_handle_int(dw_irq, EDMA_DIR_WRITE,
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dw_edma_done_interrupt,
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dw_edma_abort_interrupt);
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}
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static inline irqreturn_t dw_edma_interrupt_read(int irq, void *data)
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{
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return dw_edma_interrupt(irq, data, false);
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struct dw_edma_irq *dw_irq = data;
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return dw_edma_core_handle_int(dw_irq, EDMA_DIR_READ,
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dw_edma_done_interrupt,
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dw_edma_abort_interrupt);
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}
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static irqreturn_t dw_edma_interrupt_common(int irq, void *data)
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{
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dw_edma_interrupt(irq, data, true);
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dw_edma_interrupt(irq, data, false);
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irqreturn_t ret = IRQ_NONE;
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return IRQ_HANDLED;
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ret |= dw_edma_interrupt_write(irq, data);
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ret |= dw_edma_interrupt_read(irq, data);
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return ret;
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}
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static int dw_edma_alloc_chan_resources(struct dma_chan *dchan)
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@ -811,7 +777,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)
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vchan_init(&chan->vc, dma);
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dw_edma_v0_core_device_config(chan);
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dw_edma_core_ch_config(chan);
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}
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/* Set DMA channel capabilities */
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@ -956,14 +922,16 @@ int dw_edma_probe(struct dw_edma_chip *chip)
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dw->chip = chip;
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dw_edma_v0_core_register(dw);
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raw_spin_lock_init(&dw->lock);
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dw->wr_ch_cnt = min_t(u16, chip->ll_wr_cnt,
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dw_edma_v0_core_ch_count(dw, EDMA_DIR_WRITE));
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dw_edma_core_ch_count(dw, EDMA_DIR_WRITE));
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dw->wr_ch_cnt = min_t(u16, dw->wr_ch_cnt, EDMA_MAX_WR_CH);
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dw->rd_ch_cnt = min_t(u16, chip->ll_rd_cnt,
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dw_edma_v0_core_ch_count(dw, EDMA_DIR_READ));
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dw_edma_core_ch_count(dw, EDMA_DIR_READ));
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dw->rd_ch_cnt = min_t(u16, dw->rd_ch_cnt, EDMA_MAX_RD_CH);
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if (!dw->wr_ch_cnt && !dw->rd_ch_cnt)
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@ -982,7 +950,7 @@ int dw_edma_probe(struct dw_edma_chip *chip)
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dev_name(chip->dev));
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/* Disable eDMA, only to establish the ideal initial conditions */
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dw_edma_v0_core_off(dw);
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dw_edma_core_off(dw);
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/* Request IRQs */
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err = dw_edma_irq_request(dw, &wr_alloc, &rd_alloc);
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@ -995,7 +963,7 @@ int dw_edma_probe(struct dw_edma_chip *chip)
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goto err_irq_free;
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/* Turn debugfs on */
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dw_edma_v0_core_debugfs_on(dw);
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dw_edma_core_debugfs_on(dw);
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chip->dw = dw;
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@ -1021,7 +989,7 @@ int dw_edma_remove(struct dw_edma_chip *chip)
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return -ENODEV;
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/* Disable eDMA */
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dw_edma_v0_core_off(dw);
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dw_edma_core_off(dw);
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/* Free irqs */
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for (i = (dw->nr_irqs - 1); i >= 0; i--)
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@ -111,6 +111,21 @@ struct dw_edma {
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raw_spinlock_t lock; /* Only for legacy */
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struct dw_edma_chip *chip;
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const struct dw_edma_core_ops *core;
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};
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typedef void (*dw_edma_handler_t)(struct dw_edma_chan *);
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struct dw_edma_core_ops {
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void (*off)(struct dw_edma *dw);
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u16 (*ch_count)(struct dw_edma *dw, enum dw_edma_dir dir);
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enum dma_status (*ch_status)(struct dw_edma_chan *chan);
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irqreturn_t (*handle_int)(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,
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dw_edma_handler_t done, dw_edma_handler_t abort);
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void (*start)(struct dw_edma_chunk *chunk, bool first);
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void (*ch_config)(struct dw_edma_chan *chan);
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void (*debugfs_on)(struct dw_edma *dw);
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};
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struct dw_edma_sg {
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@ -148,4 +163,47 @@ struct dw_edma_chan *dchan2dw_edma_chan(struct dma_chan *dchan)
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return vc2dw_edma_chan(to_virt_chan(dchan));
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}
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static inline
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void dw_edma_core_off(struct dw_edma *dw)
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{
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dw->core->off(dw);
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}
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static inline
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u16 dw_edma_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
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{
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return dw->core->ch_count(dw, dir);
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}
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static inline
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enum dma_status dw_edma_core_ch_status(struct dw_edma_chan *chan)
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{
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return chan->dw->core->ch_status(chan);
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}
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static inline irqreturn_t
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dw_edma_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,
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dw_edma_handler_t done, dw_edma_handler_t abort)
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{
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return dw_irq->dw->core->handle_int(dw_irq, dir, done, abort);
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}
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static inline
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void dw_edma_core_start(struct dw_edma *dw, struct dw_edma_chunk *chunk, bool first)
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{
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dw->core->start(chunk, first);
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}
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static inline
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void dw_edma_core_ch_config(struct dw_edma_chan *chan)
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{
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chan->dw->core->ch_config(chan);
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}
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static inline
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void dw_edma_core_debugfs_on(struct dw_edma *dw)
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{
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dw->core->debugfs_on(dw);
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}
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#endif /* _DW_EDMA_CORE_H */
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@ -7,7 +7,7 @@
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*/
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#include <linux/bitfield.h>
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#include <linux/irqreturn.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include "dw-edma-core.h"
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@ -160,7 +160,7 @@ static inline u32 readl_ch(struct dw_edma *dw, enum dw_edma_dir dir, u16 ch,
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readl_ch(dw, dir, ch, &(__dw_ch_regs(dw, dir, ch)->name))
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/* eDMA management callbacks */
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void dw_edma_v0_core_off(struct dw_edma *dw)
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static void dw_edma_v0_core_off(struct dw_edma *dw)
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{
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SET_BOTH_32(dw, int_mask,
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EDMA_V0_DONE_INT_MASK | EDMA_V0_ABORT_INT_MASK);
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@ -169,7 +169,7 @@ void dw_edma_v0_core_off(struct dw_edma *dw)
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SET_BOTH_32(dw, engine_en, 0);
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}
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u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
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static u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
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{
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u32 num_ch;
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@ -186,7 +186,7 @@ u16 dw_edma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir)
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return (u16)num_ch;
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}
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enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
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static enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
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{
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struct dw_edma *dw = chan->dw;
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u32 tmp;
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@ -202,7 +202,7 @@ enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan)
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return DMA_ERROR;
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}
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void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
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static void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
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{
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struct dw_edma *dw = chan->dw;
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@ -210,7 +210,7 @@ void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan)
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FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)));
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}
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void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
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static void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
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{
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struct dw_edma *dw = chan->dw;
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@ -218,18 +218,64 @@ void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan)
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FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)));
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}
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u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir)
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static u32 dw_edma_v0_core_status_done_int(struct dw_edma *dw, enum dw_edma_dir dir)
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{
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return FIELD_GET(EDMA_V0_DONE_INT_MASK,
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GET_RW_32(dw, dir, int_status));
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}
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u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
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static u32 dw_edma_v0_core_status_abort_int(struct dw_edma *dw, enum dw_edma_dir dir)
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{
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return FIELD_GET(EDMA_V0_ABORT_INT_MASK,
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GET_RW_32(dw, dir, int_status));
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}
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static irqreturn_t
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dw_edma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir,
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dw_edma_handler_t done, dw_edma_handler_t abort)
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{
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struct dw_edma *dw = dw_irq->dw;
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unsigned long total, pos, val;
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irqreturn_t ret = IRQ_NONE;
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struct dw_edma_chan *chan;
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unsigned long off;
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u32 mask;
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if (dir == EDMA_DIR_WRITE) {
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total = dw->wr_ch_cnt;
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off = 0;
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mask = dw_irq->wr_mask;
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} else {
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total = dw->rd_ch_cnt;
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off = dw->wr_ch_cnt;
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mask = dw_irq->rd_mask;
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}
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val = dw_edma_v0_core_status_done_int(dw, dir);
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val &= mask;
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for_each_set_bit(pos, &val, total) {
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chan = &dw->chan[pos + off];
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dw_edma_v0_core_clear_done_int(chan);
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done(chan);
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ret = IRQ_HANDLED;
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}
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val = dw_edma_v0_core_status_abort_int(dw, dir);
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val &= mask;
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for_each_set_bit(pos, &val, total) {
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chan = &dw->chan[pos + off];
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dw_edma_v0_core_clear_abort_int(chan);
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abort(chan);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static void dw_edma_v0_write_ll_data(struct dw_edma_chunk *chunk, int i,
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u32 control, u32 size, u64 sar, u64 dar)
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{
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@ -300,7 +346,7 @@ static void dw_edma_v0_core_write_chunk(struct dw_edma_chunk *chunk)
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dw_edma_v0_write_ll_link(chunk, i, control, chunk->ll_region.paddr);
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}
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void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
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static void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
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{
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struct dw_edma_chan *chan = chunk->chan;
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struct dw_edma *dw = chan->dw;
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@ -371,7 +417,7 @@ void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
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FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id));
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}
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int dw_edma_v0_core_device_config(struct dw_edma_chan *chan)
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static void dw_edma_v0_core_ch_config(struct dw_edma_chan *chan)
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{
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struct dw_edma *dw = chan->dw;
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u32 tmp = 0;
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@ -438,12 +484,25 @@ int dw_edma_v0_core_device_config(struct dw_edma_chan *chan)
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SET_RW_32(dw, chan->dir, ch67_imwr_data, tmp);
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break;
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}
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return 0;
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}
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/* eDMA debugfs callbacks */
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void dw_edma_v0_core_debugfs_on(struct dw_edma *dw)
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static void dw_edma_v0_core_debugfs_on(struct dw_edma *dw)
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{
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dw_edma_v0_debugfs_on(dw);
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}
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static const struct dw_edma_core_ops dw_edma_v0_core = {
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.off = dw_edma_v0_core_off,
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.ch_count = dw_edma_v0_core_ch_count,
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.ch_status = dw_edma_v0_core_ch_status,
|
||||
.handle_int = dw_edma_v0_core_handle_int,
|
||||
.start = dw_edma_v0_core_start,
|
||||
.ch_config = dw_edma_v0_core_ch_config,
|
||||
.debugfs_on = dw_edma_v0_core_debugfs_on,
|
||||
};
|
||||
|
||||
void dw_edma_v0_core_register(struct dw_edma *dw)
|
||||
{
|
||||
dw->core = &dw_edma_v0_core;
|
||||
}
|
||||
|
||||
@ -11,17 +11,7 @@
|
||||
|
||||
#include <linux/dma/edma.h>
|
||||
|
||||
/* eDMA management callbacks */
|
||||
void dw_edma_v0_core_off(struct dw_edma *chan);
|
||||
u16 dw_edma_v0_core_ch_count(struct dw_edma *chan, enum dw_edma_dir dir);
|
||||
enum dma_status dw_edma_v0_core_ch_status(struct dw_edma_chan *chan);
|
||||
void dw_edma_v0_core_clear_done_int(struct dw_edma_chan *chan);
|
||||
void dw_edma_v0_core_clear_abort_int(struct dw_edma_chan *chan);
|
||||
u32 dw_edma_v0_core_status_done_int(struct dw_edma *chan, enum dw_edma_dir dir);
|
||||
u32 dw_edma_v0_core_status_abort_int(struct dw_edma *chan, enum dw_edma_dir dir);
|
||||
void dw_edma_v0_core_start(struct dw_edma_chunk *chunk, bool first);
|
||||
int dw_edma_v0_core_device_config(struct dw_edma_chan *chan);
|
||||
/* eDMA debug fs callbacks */
|
||||
void dw_edma_v0_core_debugfs_on(struct dw_edma *dw);
|
||||
/* eDMA core register */
|
||||
void dw_edma_v0_core_register(struct dw_edma *dw);
|
||||
|
||||
#endif /* _DW_EDMA_V0_CORE_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user