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drm/i915: Relocate intel_atomic_setup_scalers()
[ Upstream commit8976b18249] Move intel_atomic_setup_scalers() next to the other scaler code in skl_scaler.c. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com> Stable-dep-of:c3070f080f("drm/i915: Fix intel_atomic_setup_scalers() plane_state handling") Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Ville Syrjälä
Greg Kroah-Hartman
parent
2a4ef0d6e5
commit
f9954b18c4
@ -311,262 +311,6 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
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kfree(crtc_state);
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}
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static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
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int num_scalers_need, struct intel_crtc *intel_crtc,
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const char *name, int idx,
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struct intel_plane_state *plane_state,
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int *scaler_id)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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int j;
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u32 mode;
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (scaler_state->scalers[j].in_use)
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continue;
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*scaler_id = j;
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scaler_state->scalers[*scaler_id].in_use = 1;
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break;
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}
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}
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if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
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"Cannot find scaler for %s:%d\n", name, idx))
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return -EINVAL;
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/* set scaler mode */
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if (plane_state && plane_state->hw.fb &&
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plane_state->hw.fb->format->is_yuv &&
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plane_state->hw.fb->format->num_planes > 1) {
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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if (DISPLAY_VER(dev_priv) == 9) {
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mode = SKL_PS_SCALER_MODE_NV12;
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} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
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/*
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* On gen11+'s HDR planes we only use the scaler for
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* scaling. They have a dedicated chroma upsampler, so
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* we don't need the scaler to upsample the UV plane.
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*/
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mode = PS_SCALER_MODE_NORMAL;
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} else {
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struct intel_plane *linked =
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plane_state->planar_linked_plane;
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mode = PS_SCALER_MODE_PLANAR;
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if (linked)
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mode |= PS_PLANE_Y_SEL(linked->id);
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}
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} else if (DISPLAY_VER(dev_priv) >= 10) {
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mode = PS_SCALER_MODE_NORMAL;
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} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
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/*
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* when only 1 scaler is in use on a pipe with 2 scalers
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* scaler 0 operates in high quality (HQ) mode.
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* In this case use scaler 0 to take advantage of HQ mode
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*/
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scaler_state->scalers[*scaler_id].in_use = 0;
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*scaler_id = 0;
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scaler_state->scalers[0].in_use = 1;
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mode = SKL_PS_SCALER_MODE_HQ;
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} else {
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mode = SKL_PS_SCALER_MODE_DYN;
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}
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/*
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* FIXME: we should also check the scaler factors for pfit, so
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* this shouldn't be tied directly to planes.
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*/
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if (plane_state && plane_state->hw.fb) {
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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const struct drm_rect *src = &plane_state->uapi.src;
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const struct drm_rect *dst = &plane_state->uapi.dst;
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int hscale, vscale, max_vscale, max_hscale;
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/*
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* FIXME: When two scalers are needed, but only one of
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* them needs to downscale, we should make sure that
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* the one that needs downscaling support is assigned
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* as the first scaler, so we don't reject downscaling
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* unnecessarily.
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*/
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if (DISPLAY_VER(dev_priv) >= 14) {
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/*
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* On versions 14 and up, only the first
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* scaler supports a vertical scaling factor
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* of more than 1.0, while a horizontal
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* scaling factor of 3.0 is supported.
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*/
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max_hscale = 0x30000 - 1;
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if (*scaler_id == 0)
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max_vscale = 0x30000 - 1;
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else
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max_vscale = 0x10000;
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} else if (DISPLAY_VER(dev_priv) >= 10 ||
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!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
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max_hscale = 0x30000 - 1;
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max_vscale = 0x30000 - 1;
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} else {
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max_hscale = 0x20000 - 1;
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max_vscale = 0x20000 - 1;
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}
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/*
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* FIXME: We should change the if-else block above to
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* support HQ vs dynamic scaler properly.
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*/
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/* Check if required scaling is within limits */
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hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
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vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
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if (hscale < 0 || vscale < 0) {
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drm_dbg_kms(&dev_priv->drm,
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"Scaler %d doesn't support required plane scaling\n",
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*scaler_id);
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drm_rect_debug_print("src: ", src, true);
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drm_rect_debug_print("dst: ", dst, false);
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return -EINVAL;
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}
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}
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drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
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intel_crtc->pipe, *scaler_id, name, idx);
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scaler_state->scalers[*scaler_id].mode = mode;
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return 0;
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}
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/**
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* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
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* @dev_priv: i915 device
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* @intel_crtc: intel crtc
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* @crtc_state: incoming crtc_state to validate and setup scalers
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*
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* This function sets up scalers based on staged scaling requests for
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* a @crtc and its planes. It is called from crtc level check path. If request
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* is a supportable request, it attaches scalers to requested planes and crtc.
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*
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* This function takes into account the current scaler(s) in use by any planes
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* not being part of this atomic state
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*
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* Returns:
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* 0 - scalers were setup succesfully
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* error code - otherwise
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*/
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int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_plane *plane = NULL;
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struct intel_plane *intel_plane;
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struct intel_plane_state *plane_state = NULL;
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struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct drm_atomic_state *drm_state = crtc_state->uapi.state;
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struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
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int num_scalers_need;
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int i;
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num_scalers_need = hweight32(scaler_state->scaler_users);
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/*
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* High level flow:
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* - staged scaler requests are already in scaler_state->scaler_users
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* - check whether staged scaling requests can be supported
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* - add planes using scalers that aren't in current transaction
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* - assign scalers to requested users
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* - as part of plane commit, scalers will be committed
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* (i.e., either attached or detached) to respective planes in hw
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* - as part of crtc_commit, scaler will be either attached or detached
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* to crtc in hw
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*/
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/* fail if required scalers > available scalers */
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if (num_scalers_need > intel_crtc->num_scalers){
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drm_dbg_kms(&dev_priv->drm,
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"Too many scaling requests %d > %d\n",
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num_scalers_need, intel_crtc->num_scalers);
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return -EINVAL;
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}
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/* walkthrough scaler_users bits and start assigning scalers */
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for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
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int *scaler_id;
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const char *name;
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int idx, ret;
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/* skip if scaler not required */
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if (!(scaler_state->scaler_users & (1 << i)))
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continue;
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if (i == SKL_CRTC_INDEX) {
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name = "CRTC";
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idx = intel_crtc->base.base.id;
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/* panel fitter case: assign as a crtc scaler */
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scaler_id = &scaler_state->scaler_id;
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} else {
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name = "PLANE";
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/* plane scaler case: assign as a plane scaler */
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/* find the plane that set the bit as scaler_user */
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plane = drm_state->planes[i].ptr;
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/*
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* to enable/disable hq mode, add planes that are using scaler
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* into this transaction
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*/
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if (!plane) {
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struct drm_plane_state *state;
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/*
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* GLK+ scalers don't have a HQ mode so it
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* isn't necessary to change between HQ and dyn mode
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* on those platforms.
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*/
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if (DISPLAY_VER(dev_priv) >= 10)
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continue;
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plane = drm_plane_from_index(&dev_priv->drm, i);
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state = drm_atomic_get_plane_state(drm_state, plane);
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if (IS_ERR(state)) {
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drm_dbg_kms(&dev_priv->drm,
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"Failed to add [PLANE:%d] to drm_state\n",
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plane->base.id);
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return PTR_ERR(state);
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}
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}
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intel_plane = to_intel_plane(plane);
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idx = plane->base.id;
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/* plane on different crtc cannot be a scaler user of this crtc */
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if (drm_WARN_ON(&dev_priv->drm,
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intel_plane->pipe != intel_crtc->pipe))
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continue;
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plane_state = intel_atomic_get_new_plane_state(intel_state,
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intel_plane);
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scaler_id = &plane_state->scaler_id;
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}
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ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
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intel_crtc, name, idx,
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plane_state, scaler_id);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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struct drm_atomic_state *
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intel_atomic_state_alloc(struct drm_device *dev)
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{
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@ -54,8 +54,4 @@ struct intel_crtc_state *
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intel_atomic_get_crtc_state(struct drm_atomic_state *state,
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struct intel_crtc *crtc);
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int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state);
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#endif /* __INTEL_ATOMIC_H__ */
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@ -294,6 +294,263 @@ int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
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return 0;
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}
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static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
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int num_scalers_need, struct intel_crtc *intel_crtc,
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const char *name, int idx,
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struct intel_plane_state *plane_state,
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int *scaler_id)
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{
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struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
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int j;
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u32 mode;
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if (*scaler_id < 0) {
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/* find a free scaler */
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for (j = 0; j < intel_crtc->num_scalers; j++) {
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if (scaler_state->scalers[j].in_use)
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continue;
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*scaler_id = j;
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scaler_state->scalers[*scaler_id].in_use = 1;
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break;
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}
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}
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if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
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"Cannot find scaler for %s:%d\n", name, idx))
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return -EINVAL;
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/* set scaler mode */
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if (plane_state && plane_state->hw.fb &&
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plane_state->hw.fb->format->is_yuv &&
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plane_state->hw.fb->format->num_planes > 1) {
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struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
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if (DISPLAY_VER(dev_priv) == 9) {
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mode = SKL_PS_SCALER_MODE_NV12;
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} else if (icl_is_hdr_plane(dev_priv, plane->id)) {
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/*
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* On gen11+'s HDR planes we only use the scaler for
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* scaling. They have a dedicated chroma upsampler, so
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* we don't need the scaler to upsample the UV plane.
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*/
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mode = PS_SCALER_MODE_NORMAL;
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} else {
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struct intel_plane *linked =
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plane_state->planar_linked_plane;
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mode = PS_SCALER_MODE_PLANAR;
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if (linked)
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mode |= PS_PLANE_Y_SEL(linked->id);
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}
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} else if (DISPLAY_VER(dev_priv) >= 10) {
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mode = PS_SCALER_MODE_NORMAL;
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} else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
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/*
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* when only 1 scaler is in use on a pipe with 2 scalers
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* scaler 0 operates in high quality (HQ) mode.
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* In this case use scaler 0 to take advantage of HQ mode
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*/
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scaler_state->scalers[*scaler_id].in_use = 0;
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*scaler_id = 0;
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scaler_state->scalers[0].in_use = 1;
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mode = SKL_PS_SCALER_MODE_HQ;
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} else {
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mode = SKL_PS_SCALER_MODE_DYN;
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}
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/*
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* FIXME: we should also check the scaler factors for pfit, so
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* this shouldn't be tied directly to planes.
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*/
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if (plane_state && plane_state->hw.fb) {
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const struct drm_framebuffer *fb = plane_state->hw.fb;
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const struct drm_rect *src = &plane_state->uapi.src;
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const struct drm_rect *dst = &plane_state->uapi.dst;
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int hscale, vscale, max_vscale, max_hscale;
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/*
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* FIXME: When two scalers are needed, but only one of
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* them needs to downscale, we should make sure that
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* the one that needs downscaling support is assigned
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* as the first scaler, so we don't reject downscaling
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* unnecessarily.
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*/
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if (DISPLAY_VER(dev_priv) >= 14) {
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/*
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* On versions 14 and up, only the first
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* scaler supports a vertical scaling factor
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* of more than 1.0, while a horizontal
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* scaling factor of 3.0 is supported.
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*/
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max_hscale = 0x30000 - 1;
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if (*scaler_id == 0)
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max_vscale = 0x30000 - 1;
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else
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max_vscale = 0x10000;
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} else if (DISPLAY_VER(dev_priv) >= 10 ||
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!intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
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max_hscale = 0x30000 - 1;
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max_vscale = 0x30000 - 1;
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} else {
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max_hscale = 0x20000 - 1;
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max_vscale = 0x20000 - 1;
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}
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/*
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* FIXME: We should change the if-else block above to
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* support HQ vs dynamic scaler properly.
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*/
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/* Check if required scaling is within limits */
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hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
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vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
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if (hscale < 0 || vscale < 0) {
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drm_dbg_kms(&dev_priv->drm,
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"Scaler %d doesn't support required plane scaling\n",
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*scaler_id);
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drm_rect_debug_print("src: ", src, true);
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drm_rect_debug_print("dst: ", dst, false);
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return -EINVAL;
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}
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}
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drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
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intel_crtc->pipe, *scaler_id, name, idx);
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scaler_state->scalers[*scaler_id].mode = mode;
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return 0;
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}
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/**
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* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
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* @dev_priv: i915 device
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* @intel_crtc: intel crtc
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* @crtc_state: incoming crtc_state to validate and setup scalers
|
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*
|
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* This function sets up scalers based on staged scaling requests for
|
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* a @crtc and its planes. It is called from crtc level check path. If request
|
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* is a supportable request, it attaches scalers to requested planes and crtc.
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*
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* This function takes into account the current scaler(s) in use by any planes
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* not being part of this atomic state
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*
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* Returns:
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* 0 - scalers were setup successfully
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* error code - otherwise
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*/
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int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
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struct intel_crtc *intel_crtc,
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struct intel_crtc_state *crtc_state)
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{
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struct drm_plane *plane = NULL;
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struct intel_plane *intel_plane;
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struct intel_plane_state *plane_state = NULL;
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struct intel_crtc_scaler_state *scaler_state =
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&crtc_state->scaler_state;
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struct drm_atomic_state *drm_state = crtc_state->uapi.state;
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||||
struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
|
||||
int num_scalers_need;
|
||||
int i;
|
||||
|
||||
num_scalers_need = hweight32(scaler_state->scaler_users);
|
||||
|
||||
/*
|
||||
* High level flow:
|
||||
* - staged scaler requests are already in scaler_state->scaler_users
|
||||
* - check whether staged scaling requests can be supported
|
||||
* - add planes using scalers that aren't in current transaction
|
||||
* - assign scalers to requested users
|
||||
* - as part of plane commit, scalers will be committed
|
||||
* (i.e., either attached or detached) to respective planes in hw
|
||||
* - as part of crtc_commit, scaler will be either attached or detached
|
||||
* to crtc in hw
|
||||
*/
|
||||
|
||||
/* fail if required scalers > available scalers */
|
||||
if (num_scalers_need > intel_crtc->num_scalers) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Too many scaling requests %d > %d\n",
|
||||
num_scalers_need, intel_crtc->num_scalers);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* walkthrough scaler_users bits and start assigning scalers */
|
||||
for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
|
||||
int *scaler_id;
|
||||
const char *name;
|
||||
int idx, ret;
|
||||
|
||||
/* skip if scaler not required */
|
||||
if (!(scaler_state->scaler_users & (1 << i)))
|
||||
continue;
|
||||
|
||||
if (i == SKL_CRTC_INDEX) {
|
||||
name = "CRTC";
|
||||
idx = intel_crtc->base.base.id;
|
||||
|
||||
/* panel fitter case: assign as a crtc scaler */
|
||||
scaler_id = &scaler_state->scaler_id;
|
||||
} else {
|
||||
name = "PLANE";
|
||||
|
||||
/* plane scaler case: assign as a plane scaler */
|
||||
/* find the plane that set the bit as scaler_user */
|
||||
plane = drm_state->planes[i].ptr;
|
||||
|
||||
/*
|
||||
* to enable/disable hq mode, add planes that are using scaler
|
||||
* into this transaction
|
||||
*/
|
||||
if (!plane) {
|
||||
struct drm_plane_state *state;
|
||||
|
||||
/*
|
||||
* GLK+ scalers don't have a HQ mode so it
|
||||
* isn't necessary to change between HQ and dyn mode
|
||||
* on those platforms.
|
||||
*/
|
||||
if (DISPLAY_VER(dev_priv) >= 10)
|
||||
continue;
|
||||
|
||||
plane = drm_plane_from_index(&dev_priv->drm, i);
|
||||
state = drm_atomic_get_plane_state(drm_state, plane);
|
||||
if (IS_ERR(state)) {
|
||||
drm_dbg_kms(&dev_priv->drm,
|
||||
"Failed to add [PLANE:%d] to drm_state\n",
|
||||
plane->base.id);
|
||||
return PTR_ERR(state);
|
||||
}
|
||||
}
|
||||
|
||||
intel_plane = to_intel_plane(plane);
|
||||
idx = plane->base.id;
|
||||
|
||||
/* plane on different crtc cannot be a scaler user of this crtc */
|
||||
if (drm_WARN_ON(&dev_priv->drm,
|
||||
intel_plane->pipe != intel_crtc->pipe))
|
||||
continue;
|
||||
|
||||
plane_state = intel_atomic_get_new_plane_state(intel_state,
|
||||
intel_plane);
|
||||
scaler_id = &plane_state->scaler_id;
|
||||
}
|
||||
|
||||
ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
|
||||
intel_crtc, name, idx,
|
||||
plane_state, scaler_id);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int glk_coef_tap(int i)
|
||||
{
|
||||
return i % 7;
|
||||
|
||||
@ -8,17 +8,22 @@
|
||||
#include <linux/types.h>
|
||||
|
||||
enum drm_scaling_filter;
|
||||
struct drm_i915_private;
|
||||
struct intel_crtc_state;
|
||||
struct intel_plane_state;
|
||||
struct intel_plane;
|
||||
enum pipe;
|
||||
struct drm_i915_private;
|
||||
struct intel_crtc;
|
||||
struct intel_crtc_state;
|
||||
struct intel_plane;
|
||||
struct intel_plane_state;
|
||||
|
||||
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
|
||||
|
||||
int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
|
||||
struct intel_plane_state *plane_state);
|
||||
|
||||
int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
|
||||
struct intel_crtc *intel_crtc,
|
||||
struct intel_crtc_state *crtc_state);
|
||||
|
||||
void skl_pfit_enable(const struct intel_crtc_state *crtc_state);
|
||||
|
||||
void skl_program_plane_scaler(struct intel_plane *plane,
|
||||
@ -26,4 +31,5 @@ void skl_program_plane_scaler(struct intel_plane *plane,
|
||||
const struct intel_plane_state *plane_state);
|
||||
void skl_detach_scalers(const struct intel_crtc_state *crtc_state);
|
||||
void skl_scaler_disable(const struct intel_crtc_state *old_crtc_state);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user