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rtw88: 8822c: reorder macro position according to the register number
This patch doesn't change logic at all, just a refactor patch. 1. Move BIT MASK and BIT definition along with the register definition 2. Remove redundant definition 3. Align macros with Tab key Signed-off-by: Guo-Feng Fan <vincent_fann@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org> Link: https://lore.kernel.org/r/20210419003748.3224-2-pkshih@realtek.com
This commit is contained in:
Guo-Feng Fan
Kalle Valo
parent
a926c025d5
commit
f98bf9ee63
@ -1095,13 +1095,13 @@ static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
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if (pg_pa_bias == EFUSE_READ_FAIL)
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return;
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pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
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rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias);
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rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);
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}
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for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
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rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
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&pg_pa_bias);
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pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
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rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias);
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rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);
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}
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}
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@ -2546,9 +2546,9 @@ static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
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rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
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rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
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if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
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rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
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rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
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else
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rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
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rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
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rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
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rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
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}
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@ -2566,11 +2566,11 @@ static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
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rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
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rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
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rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0);
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rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
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rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
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if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
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rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1);
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rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
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rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
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} else {
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rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
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@ -3317,9 +3317,9 @@ static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
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rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
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0x8 | (path << 1));
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if (dpk_info->dpk_band == RTW_BAND_2G)
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rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000);
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rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
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else
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rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000);
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rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
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rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
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@ -164,180 +164,185 @@ const struct rtw_table name ## _tbl = { \
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#define REG_ANAPARLDO_POW_MAC 0x0029
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#define BIT_LDOE25_PON BIT(0)
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#define XCAP_MASK GENMASK(6, 0)
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#define CFO_TRK_ENABLE_TH 20
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#define CFO_TRK_STOP_TH 10
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#define CFO_TRK_ADJ_TH 10
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#define REG_TXDFIR0 0x808
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#define REG_DFIRBW 0x810
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#define REG_ANTMAP0 0x820
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#define REG_ANTMAP 0x824
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#define REG_DYMPRITH 0x86c
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#define REG_DYMENTH0 0x870
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#define REG_DYMENTH 0x874
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#define REG_SBD 0x88c
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#define REG_TXDFIR0 0x808
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#define REG_DFIRBW 0x810
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#define REG_ANTMAP0 0x820
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#define REG_ANTMAP 0x824
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#define REG_DYMPRITH 0x86c
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#define REG_DYMENTH0 0x870
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#define REG_DYMENTH 0x874
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#define REG_SBD 0x88c
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#define BITS_SUBTUNE GENMASK(15, 12)
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#define REG_DYMTHMIN 0x8a4
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#define REG_TXBWCTL 0x9b0
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#define REG_TXCLK 0x9b4
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#define REG_SCOTRK 0xc30
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#define REG_MRCM 0xc38
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#define REG_AGCSWSH 0xc44
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#define REG_ANTWTPD 0xc54
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#define REG_PT_CHSMO 0xcbc
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#define REG_DYMTHMIN 0x8a4
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#define REG_TXBWCTL 0x9b0
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#define REG_TXCLK 0x9b4
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#define REG_SCOTRK 0xc30
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#define REG_MRCM 0xc38
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#define REG_AGCSWSH 0xc44
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#define REG_ANTWTPD 0xc54
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#define REG_PT_CHSMO 0xcbc
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#define BIT_PT_OPT BIT(21)
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#define REG_ORITXCODE 0x1800
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#define REG_3WIRE 0x180c
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#define REG_ORITXCODE 0x1800
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#define REG_3WIRE 0x180c
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#define BIT_3WIRE_TX_EN BIT(0)
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#define BIT_3WIRE_RX_EN BIT(1)
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#define BIT_3WIRE_PI_ON BIT(28)
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#define REG_ANAPAR_A 0x1830
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#define REG_ANAPAR_A 0x1830
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#define BIT_ANAPAR_UPDATE BIT(29)
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#define REG_RXAGCCTL0 0x18ac
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#define REG_RXAGCCTL0 0x18ac
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#define BITS_RXAGC_CCK GENMASK(15, 12)
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#define BITS_RXAGC_OFDM GENMASK(8, 4)
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#define REG_DCKA_I_0 0x18bc
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#define REG_DCKA_I_1 0x18c0
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#define REG_DCKA_Q_0 0x18d8
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#define REG_DCKA_Q_1 0x18dc
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#define REG_CCKSB 0x1a00
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#define REG_RXCCKSEL 0x1a04
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#define REG_BGCTRL 0x1a14
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#define REG_DCKA_I_0 0x18bc
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#define REG_DCKA_I_1 0x18c0
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#define REG_DCKA_Q_0 0x18d8
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#define REG_DCKA_Q_1 0x18dc
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#define REG_CCKSB 0x1a00
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#define REG_RXCCKSEL 0x1a04
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#define REG_BGCTRL 0x1a14
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#define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9))
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#define REG_TXF0 0x1a20
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#define REG_TXF1 0x1a24
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#define REG_TXF2 0x1a28
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#define REG_CCANRX 0x1a2c
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#define REG_TXF0 0x1a20
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#define REG_TXF1 0x1a24
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#define REG_TXF2 0x1a28
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#define REG_CCANRX 0x1a2c
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#define BIT_CCK_FA_RST (BIT(14) | BIT(15))
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#define BIT_OFDM_FA_RST (BIT(12) | BIT(13))
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#define REG_CCK_FACNT 0x1a5c
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#define REG_CCKTXONLY 0x1a80
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#define REG_CCK_FACNT 0x1a5c
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#define REG_CCKTXONLY 0x1a80
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#define BIT_BB_CCK_CHECK_EN BIT(18)
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#define REG_TXF3 0x1a98
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#define REG_TXF4 0x1a9c
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#define REG_TXF5 0x1aa0
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#define REG_TXF6 0x1aac
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#define REG_TXF7 0x1ab0
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#define REG_CCK_SOURCE 0x1abc
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#define REG_TXF3 0x1a98
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#define REG_TXF4 0x1a9c
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#define REG_TXF5 0x1aa0
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#define REG_TXF6 0x1aac
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#define REG_TXF7 0x1ab0
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#define REG_CCK_SOURCE 0x1abc
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#define BIT_NBI_EN BIT(30)
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#define REG_IQKSTAT 0x1b10
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#define REG_TXANT 0x1c28
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#define REG_ENCCK 0x1c3c
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#define BIT_CCK_BLK_EN BIT(1)
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#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
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#define REG_CCAMSK 0x1c80
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#define REG_RSTB 0x1c90
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#define BIT_RSTB_3WIRE BIT(8)
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#define REG_RX_BREAK 0x1d2c
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#define BIT_COM_RX_GCK_EN BIT(31)
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#define REG_RXFNCTL 0x1d30
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#define REG_RXIGI 0x1d70
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#define REG_ENFN 0x1e24
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#define REG_TXANTSEG 0x1e28
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#define REG_TXLGMAP 0x1e2c
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#define REG_CCKPATH 0x1e5c
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#define REG_CNT_CTRL 0x1eb4
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#define BIT_ALL_CNT_RST BIT(25)
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#define REG_OFDM_FACNT 0x2d00
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#define REG_OFDM_FACNT1 0x2d04
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#define REG_OFDM_FACNT2 0x2d08
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#define REG_OFDM_FACNT3 0x2d0c
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#define REG_OFDM_FACNT4 0x2d10
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#define REG_OFDM_FACNT5 0x2d20
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#define REG_RPT_CIP 0x2d9c
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#define REG_OFDM_TXCNT 0x2de0
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#define REG_ORITXCODE2 0x4100
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#define REG_3WIRE2 0x410c
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#define REG_ANAPAR_B 0x4130
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#define REG_RXAGCCTL 0x41ac
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#define REG_DCKB_I_0 0x41bc
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#define REG_DCKB_I_1 0x41c0
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#define REG_DCKB_Q_0 0x41d8
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#define REG_DCKB_Q_1 0x41dc
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#define RF_MODE_TRXAGC 0x00
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#define RF_RXAGC_OFFSET 0x19
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#define RF_BW_TRXBB 0x1a
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#define RF_TX_GAIN_OFFSET 0x55
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#define RF_TX_GAIN 0x56
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#define RF_TXA_LB_SW 0x63
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#define RF_RXG_GAIN 0x87
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#define RF_RXA_MIX_GAIN 0x8a
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#define RF_EXT_TIA_BW 0x8f
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#define RF_DEBUG 0xde
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#define REG_NCTL0 0x1b00
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#define BIT_SUBPAGE GENMASK(3, 0)
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#define REG_DPD_CTL0_S0 0x1b04
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#define BIT_GS_PWSF GENMASK(27, 0)
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#define REG_DPD_CTL1_S0 0x1b08
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#define BIT_DPD_EN BIT(31)
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#define REG_IQKSTAT 0x1b10
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#define REG_IQK_CTL1 0x1b20
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#define BIT_BYPASS_DPD BIT(25)
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#define BIT_TX_CFIR GENMASK(31, 30)
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#define REG_DPD_LUT0 0x1b44
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#define BIT_GLOSS_DB GENMASK(14, 12)
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#define REG_DPD_CTL0_S1 0x1b5c
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#define REG_DPD_LUT3 0x1b60
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#define REG_DPD_CTL1_S1 0x1b60
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#define REG_DPD_AGC 0x1b67
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#define REG_DPD_CTL0 0x1bb4
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#define REG_R_CONFIG 0x1bcc
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#define BIT_INNER_LB BIT(21)
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#define BIT_IQ_SWITCH GENMASK(5, 0)
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#define REG_RXSRAM_CTL 0x1bd4
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#define BIT_RPT_SEL GENMASK(20, 16)
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#define BIT_DPD_CLK GENMASK(7, 4)
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#define REG_DPD_CTL11 0x1be4
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#define REG_DPD_CTL12 0x1be8
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#define REG_DPD_CTL15 0x1bf4
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#define REG_DPD_CTL16 0x1bf8
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#define REG_STAT_RPT 0x1bfc
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#define BIT_EXT_TIA_BW BIT(1)
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#define BIT_DE_TRXBW BIT(2)
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#define BIT_DE_TX_GAIN BIT(16)
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#define BIT_RXG_GAIN BIT(18)
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#define BIT_DE_PWR_TRIM BIT(19)
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#define BIT_INNER_LB BIT(21)
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#define BIT_BYPASS_DPD BIT(25)
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#define BIT_DPD_EN BIT(31)
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#define BIT_SUBPAGE GENMASK(3, 0)
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#define BIT_TXAGC GENMASK(4, 0)
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#define BIT_GAIN_TXBB GENMASK(4, 0)
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#define BIT_LB_ATT GENMASK(4, 2)
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#define BIT_RXA_MIX_GAIN GENMASK(4, 3)
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#define BIT_IQ_SWITCH GENMASK(5, 0)
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#define BIT_DPD_CLK GENMASK(7, 4)
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#define BIT_RXAGC GENMASK(9, 5)
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#define BIT_BW_RXBB GENMASK(11, 10)
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#define BIT_LB_SW GENMASK(13, 12)
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#define BIT_BW_TXBB GENMASK(14, 12)
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#define BIT_GLOSS_DB GENMASK(14, 12)
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#define BIT_TXA_LB_ATT GENMASK(15, 14)
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#define BIT_TX_OFFSET_VAL GENMASK(18, 14)
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#define BIT_RPT_SEL GENMASK(20, 16)
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#define BIT_GS_PWSF GENMASK(27, 0)
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#define BIT_RPT_DGAIN GENMASK(27, 16)
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#define BIT_TX_CFIR GENMASK(31, 30)
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#define PPG_THERMAL_A 0x1ef
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#define PPG_THERMAL_B 0x1b0
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#define RF_THEMAL_MASK GENMASK(19, 16)
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#define PPG_2GL_TXAB 0x1d4
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#define PPG_2GM_TXAB 0x1ee
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#define PPG_2GH_TXAB 0x1d2
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#define PPG_2G_A_MASK GENMASK(3, 0)
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#define PPG_2G_B_MASK GENMASK(7, 4)
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#define PPG_5GL1_TXA 0x1ec
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#define PPG_5GL2_TXA 0x1e8
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#define PPG_5GM1_TXA 0x1e4
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#define PPG_5GM2_TXA 0x1e0
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#define PPG_5GH1_TXA 0x1dc
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#define PPG_5GL1_TXB 0x1eb
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#define PPG_5GL2_TXB 0x1e7
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#define PPG_5GM1_TXB 0x1e3
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#define PPG_5GM2_TXB 0x1df
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#define PPG_5GH1_TXB 0x1db
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#define PPG_5G_MASK GENMASK(4, 0)
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#define PPG_PABIAS_2GA 0x1d6
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#define PPG_PABIAS_2GB 0x1d5
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#define PPG_PABIAS_5GA 0x1d8
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#define PPG_PABIAS_5GB 0x1d7
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#define PPG_PABIAS_MASK GENMASK(3, 0)
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#define RF_PABIAS_2G_MASK GENMASK(15, 12)
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#define RF_PABIAS_5G_MASK GENMASK(19, 16)
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#define REG_TXANT 0x1c28
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#define REG_ENCCK 0x1c3c
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#define BIT_CCK_BLK_EN BIT(1)
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#define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1))
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#define REG_CCAMSK 0x1c80
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#define REG_RSTB 0x1c90
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#define BIT_RSTB_3WIRE BIT(8)
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#define REG_RX_BREAK 0x1d2c
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#define BIT_COM_RX_GCK_EN BIT(31)
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#define REG_RXFNCTL 0x1d30
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#define REG_RXIGI 0x1d70
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#define REG_ENFN 0x1e24
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#define REG_TXANTSEG 0x1e28
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#define REG_TXLGMAP 0x1e2c
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#define REG_CCKPATH 0x1e5c
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#define REG_CNT_CTRL 0x1eb4
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#define BIT_ALL_CNT_RST BIT(25)
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#define REG_OFDM_FACNT 0x2d00
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#define REG_OFDM_FACNT1 0x2d04
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#define REG_OFDM_FACNT2 0x2d08
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#define REG_OFDM_FACNT3 0x2d0c
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#define REG_OFDM_FACNT4 0x2d10
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#define REG_OFDM_FACNT5 0x2d20
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#define REG_RPT_CIP 0x2d9c
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#define REG_OFDM_TXCNT 0x2de0
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#define REG_ORITXCODE2 0x4100
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#define REG_3WIRE2 0x410c
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#define REG_ANAPAR_B 0x4130
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#define REG_RXAGCCTL 0x41ac
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#define REG_DCKB_I_0 0x41bc
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#define REG_DCKB_I_1 0x41c0
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#define REG_DCKB_Q_0 0x41d8
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#define REG_DCKB_Q_1 0x41dc
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#define RF_MODE_TRXAGC 0x00
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#define BIT_RXAGC GENMASK(9, 5)
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#define BIT_TXAGC GENMASK(4, 0)
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#define RF_RXAGC_OFFSET 0x19
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#define RF_BW_TRXBB 0x1a
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#define BIT_BW_TXBB GENMASK(14, 12)
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#define BIT_BW_RXBB GENMASK(11, 10)
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#define RF_TX_GAIN_OFFSET 0x55
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#define BIT_BB_GAIN GENMASK(18, 14)
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#define BIT_RF_GAIN GENMASK(4, 2)
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#define RF_TX_GAIN 0x56
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#define BIT_GAIN_TXBB GENMASK(4, 0)
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#define RF_PA 0x60
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#define RF_PABIAS_2G_MASK GENMASK(15, 12)
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#define RF_PABIAS_5G_MASK GENMASK(19, 16)
|
||||
#define RF_TXA_LB_SW 0x63
|
||||
#define BIT_TXA_LB_ATT GENMASK(15, 14)
|
||||
#define BIT_LB_SW GENMASK(13, 12)
|
||||
#define BIT_LB_ATT GENMASK(4, 2)
|
||||
#define RF_RXG_GAIN 0x87
|
||||
#define BIT_RXG_GAIN BIT(18)
|
||||
#define RF_RXA_MIX_GAIN 0x8a
|
||||
#define BIT_RXA_MIX_GAIN GENMASK(4, 3)
|
||||
#define RF_EXT_TIA_BW 0x8f
|
||||
#define RF_DEBUG 0xde
|
||||
#define BIT_DE_PWR_TRIM BIT(19)
|
||||
#define BIT_DE_TX_GAIN BIT(16)
|
||||
#define BIT_DE_TRXBW BIT(2)
|
||||
|
||||
#define PPG_THERMAL_B 0x1b0
|
||||
#define RF_THEMAL_MASK GENMASK(19, 16)
|
||||
#define PPG_2GH_TXAB 0x1d2
|
||||
#define PPG_2G_A_MASK GENMASK(3, 0)
|
||||
#define PPG_2G_B_MASK GENMASK(7, 4)
|
||||
#define PPG_2GL_TXAB 0x1d4
|
||||
#define PPG_PABIAS_2GB 0x1d5
|
||||
#define PPG_PABIAS_2GA 0x1d6
|
||||
#define PPG_PABIAS_MASK GENMASK(3, 0)
|
||||
#define PPG_PABIAS_5GB 0x1d7
|
||||
#define PPG_PABIAS_5GA 0x1d8
|
||||
#define PPG_5G_MASK GENMASK(4, 0)
|
||||
#define PPG_5GH1_TXB 0x1db
|
||||
#define PPG_5GH1_TXA 0x1dc
|
||||
#define PPG_5GM2_TXB 0x1df
|
||||
#define PPG_5GM2_TXA 0x1e0
|
||||
#define PPG_5GM1_TXB 0x1e3
|
||||
#define PPG_5GM1_TXA 0x1e4
|
||||
#define PPG_5GL2_TXB 0x1e7
|
||||
#define PPG_5GL2_TXA 0x1e8
|
||||
#define PPG_5GL1_TXB 0x1eb
|
||||
#define PPG_5GL1_TXA 0x1ec
|
||||
#define PPG_2GM_TXAB 0x1ee
|
||||
#define PPG_THERMAL_A 0x1ef
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user