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spi: pxa2xx: Update documentation to point out that it's outdated
Update documentation by pointing out that it's applicable mostly for a legacy platform. While at it, add couple of points with regard to ACPI, Device Tree, and automatic DMA enablement. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210517140351.901-9-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Andy Shevchenko
Mark Brown
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8083d6b812
commit
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@ -2,43 +2,47 @@
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PXA2xx SPI on SSP driver HOWTO
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==============================
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This a mini howto on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into a SPI master controller
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This a mini HOWTO on the pxa2xx_spi driver. The driver turns a PXA2xx
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synchronous serial port into an SPI master controller
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(see Documentation/spi/spi-summary.rst). The driver has the following features
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- Support for any PXA2xx SSP
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- Support for any PXA2xx and compatible SSP.
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- SSP PIO and SSP DMA data transfers.
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- External and Internal (SSPFRM) chip selects.
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- Per slave device (chip) configuration.
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- Full suspend, freeze, resume support.
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The driver is built around a "spi_message" fifo serviced by workqueue and a
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tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
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(pump_transfer) is responsible for queuing SPI transactions and setting up and
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launching the dma/interrupt driven transfers.
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The driver is built around a &struct spi_message FIFO serviced by kernel
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thread. The kernel thread, spi_pump_messages(), drives message FIFO and
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is responsible for queuing SPI transactions and setting up and launching
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the DMA or interrupt driven transfers.
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Declaring PXA2xx Master Controllers
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-----------------------------------
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Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
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"platform device". The master configuration is passed to the driver via a table
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found in include/linux/spi/pxa2xx_spi.h::
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Typically, for a legacy platform, an SPI master is defined in the
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arch/.../mach-*/board-*.c as a "platform device". The master configuration
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is passed to the driver via a table found in include/linux/spi/pxa2xx_spi.h::
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struct pxa2xx_spi_controller {
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u16 num_chipselect;
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u8 enable_dma;
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...
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};
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The "pxa2xx_spi_controller.num_chipselect" field is used to determine the number of
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slave device (chips) attached to this SPI master.
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The "pxa2xx_spi_controller.enable_dma" field informs the driver that SSP DMA should
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be used. This caused the driver to acquire two DMA channels: rx_channel and
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tx_channel. The rx_channel has a higher DMA service priority the tx_channel.
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be used. This caused the driver to acquire two DMA channels: Rx channel and
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Tx channel. The Rx channel has a higher DMA service priority than the Tx channel.
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See the "PXA2xx Developer Manual" section "DMA Controller".
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For the new platforms the description of the controller and peripheral devices
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comes from Device Tree or ACPI.
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NSSP MASTER SAMPLE
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------------------
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Below is a sample configuration using the PXA255 NSSP::
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Below is a sample configuration using the PXA255 NSSP for a legacy platform::
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static struct resource pxa_spi_nssp_resources[] = {
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[0] = {
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@ -79,9 +83,10 @@ Below is a sample configuration using the PXA255 NSSP::
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Declaring Slave Devices
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-----------------------
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Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
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using the "spi_board_info" structure found in "linux/spi/spi.h". See
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"Documentation/spi/spi-summary.rst" for additional information.
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Typically, for a legacy platform, each SPI slave (chip) is defined in the
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arch/.../mach-*/board-*.c using the "spi_board_info" structure found in
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"linux/spi/spi.h". See "Documentation/spi/spi-summary.rst" for additional
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information.
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Each slave device attached to the PXA must provide slave specific configuration
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information via the structure "pxa2xx_spi_chip" found in
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@ -101,9 +106,9 @@ device. All fields are optional.
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};
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The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
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used to configure the SSP hardware fifo. These fields are critical to the
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used to configure the SSP hardware FIFO. These fields are critical to the
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performance of pxa2xx_spi driver and misconfiguration will result in rx
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fifo overruns (especially in PIO mode transfers). Good default values are::
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FIFO overruns (especially in PIO mode transfers). Good default values are::
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.tx_threshold = 8,
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.rx_threshold = 8,
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@ -118,7 +123,7 @@ use a value of 8. The driver will determine a reasonable default if
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dma_burst_size == 0.
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The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
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trailing bytes in the SSP receiver fifo. The correct value for this field is
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trailing bytes in the SSP receiver FIFO. The correct value for this field is
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dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
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slave device. Please note that the PXA2xx SSP 1 does not support trailing byte
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timeouts and must busy-wait any trailing bytes.
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@ -131,19 +136,19 @@ testing.
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The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
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function for asserting/deasserting a slave device chip select. If the field is
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NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
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configured to use SSPFRM instead.
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configured to use GPIO or SSPFRM instead.
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NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
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chipselect is dropped after each spi_transfer. Most devices need chip select
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asserted around the complete message. Use SSPFRM as a GPIO (through cs_control)
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asserted around the complete message. Use SSPFRM as a GPIO (through a descriptor)
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to accommodate these chips.
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NSSP SLAVE SAMPLE
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-----------------
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The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
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"spi_board_info.controller_data" field. Below is a sample configuration using
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the PXA255 NSSP.
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For a legacy platform or in some other cases, the pxa2xx_spi_chip structure
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is passed to the pxa2xx_spi driver in the "spi_board_info.controller_data"
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field. Below is a sample configuration using the PXA255 NSSP.
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::
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@ -212,7 +217,9 @@ DMA and PIO I/O Support
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-----------------------
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The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
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transfers. The driver defaults to PIO mode and DMA transfers must be enabled
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by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure. The DMA
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by setting the "enable_dma" flag in the "pxa2xx_spi_controller" structure.
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For the newer platforms, that are known to support DMA, the driver will enable
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it automatically and try it first with a possible fallback to PIO. The DMA
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mode supports both coherent and stream based DMA mappings.
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The following logic is used to determine the type of I/O to be used on
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@ -236,5 +243,4 @@ a per "spi_transfer" basis::
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THANKS TO
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---------
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David Brownell and others for mentoring the development of this driver.
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