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mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.
This adds the mmc host driver for the Synopsys DesignWare mmc host controller, found in a number of embedded SoC designs. Signed-off-by: Will Newton <will.newton@imgtec.com> Reviewed-by: Matt Fleming <matt@console-pimps.org> Reviewed-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
parent
03d2bfc878
commit
f95f3850f7
@ -479,6 +479,22 @@ config SDH_BFIN_MISSING_CMD_PULLUP_WORKAROUND
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help
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If you say yes here SD-Cards may work on the EZkit.
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config MMC_DW
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tristate "Synopsys DesignWare Memory Card Interface"
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depends on ARM
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help
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This selects support for the Synopsys DesignWare Mobile Storage IP
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block, this provides host support for SD and MMC interfaces, in both
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PIO and external DMA modes.
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config MMC_DW_IDMAC
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bool "Internal DMAC interface"
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depends on MMC_DW
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help
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This selects support for the internal DMAC block within the Synopsys
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Designware Mobile Storage IP block. This disables the external DMA
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interface.
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config MMC_SH_MMCIF
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tristate "SuperH Internal MMCIF support"
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depends on MMC_BLOCK && (SUPERH || ARCH_SHMOBILE)
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@ -31,6 +31,7 @@ obj-$(CONFIG_MMC_TMIO) += tmio_mmc.o
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obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
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obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
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obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o
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obj-$(CONFIG_MMC_DW) += dw_mmc.o
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obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
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obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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obj-$(CONFIG_MMC_USHC) += ushc.o
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1796
drivers/mmc/host/dw_mmc.c
Normal file
1796
drivers/mmc/host/dw_mmc.c
Normal file
File diff suppressed because it is too large
Load Diff
168
drivers/mmc/host/dw_mmc.h
Normal file
168
drivers/mmc/host/dw_mmc.h
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@ -0,0 +1,168 @@
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/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _DW_MMC_H_
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#define _DW_MMC_H_
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#define SDMMC_CTRL 0x000
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#define SDMMC_PWREN 0x004
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#define SDMMC_CLKDIV 0x008
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#define SDMMC_CLKSRC 0x00c
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#define SDMMC_CLKENA 0x010
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#define SDMMC_TMOUT 0x014
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#define SDMMC_CTYPE 0x018
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#define SDMMC_BLKSIZ 0x01c
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#define SDMMC_BYTCNT 0x020
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#define SDMMC_INTMASK 0x024
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#define SDMMC_CMDARG 0x028
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#define SDMMC_CMD 0x02c
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#define SDMMC_RESP0 0x030
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#define SDMMC_RESP1 0x034
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#define SDMMC_RESP2 0x038
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#define SDMMC_RESP3 0x03c
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#define SDMMC_MINTSTS 0x040
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#define SDMMC_RINTSTS 0x044
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#define SDMMC_STATUS 0x048
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#define SDMMC_FIFOTH 0x04c
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#define SDMMC_CDETECT 0x050
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#define SDMMC_WRTPRT 0x054
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#define SDMMC_GPIO 0x058
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#define SDMMC_TCBCNT 0x05c
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#define SDMMC_TBBCNT 0x060
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#define SDMMC_DEBNCE 0x064
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#define SDMMC_USRID 0x068
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#define SDMMC_VERID 0x06c
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#define SDMMC_HCON 0x070
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#define SDMMC_BMOD 0x080
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#define SDMMC_PLDMND 0x084
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#define SDMMC_DBADDR 0x088
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#define SDMMC_IDSTS 0x08c
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#define SDMMC_IDINTEN 0x090
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#define SDMMC_DSCADDR 0x094
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#define SDMMC_BUFADDR 0x098
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#define SDMMC_DATA 0x100
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#define SDMMC_DATA_ADR 0x100
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/* shift bit field */
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#define _SBF(f, v) ((v) << (f))
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/* Control register defines */
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#define SDMMC_CTRL_USE_IDMAC BIT(25)
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#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
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#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
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#define SDMMC_CTRL_SEND_CCSD BIT(9)
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#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
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#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
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#define SDMMC_CTRL_READ_WAIT BIT(6)
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#define SDMMC_CTRL_DMA_ENABLE BIT(5)
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#define SDMMC_CTRL_INT_ENABLE BIT(4)
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#define SDMMC_CTRL_DMA_RESET BIT(2)
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#define SDMMC_CTRL_FIFO_RESET BIT(1)
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#define SDMMC_CTRL_RESET BIT(0)
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/* Clock Enable register defines */
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#define SDMMC_CLKEN_LOW_PWR BIT(16)
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#define SDMMC_CLKEN_ENABLE BIT(0)
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/* time-out register defines */
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#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
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#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
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#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
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#define SDMMC_TMOUT_RESP_MSK 0xFF
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/* card-type register defines */
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#define SDMMC_CTYPE_8BIT BIT(16)
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#define SDMMC_CTYPE_4BIT BIT(0)
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#define SDMMC_CTYPE_1BIT 0
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/* Interrupt status & mask register defines */
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#define SDMMC_INT_SDIO BIT(16)
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#define SDMMC_INT_EBE BIT(15)
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#define SDMMC_INT_ACD BIT(14)
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#define SDMMC_INT_SBE BIT(13)
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#define SDMMC_INT_HLE BIT(12)
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#define SDMMC_INT_FRUN BIT(11)
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#define SDMMC_INT_HTO BIT(10)
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#define SDMMC_INT_DTO BIT(9)
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#define SDMMC_INT_RTO BIT(8)
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#define SDMMC_INT_DCRC BIT(7)
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#define SDMMC_INT_RCRC BIT(6)
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#define SDMMC_INT_RXDR BIT(5)
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#define SDMMC_INT_TXDR BIT(4)
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#define SDMMC_INT_DATA_OVER BIT(3)
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#define SDMMC_INT_CMD_DONE BIT(2)
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#define SDMMC_INT_RESP_ERR BIT(1)
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#define SDMMC_INT_CD BIT(0)
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#define SDMMC_INT_ERROR 0xbfc2
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/* Command register defines */
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#define SDMMC_CMD_START BIT(31)
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#define SDMMC_CMD_CCS_EXP BIT(23)
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#define SDMMC_CMD_CEATA_RD BIT(22)
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#define SDMMC_CMD_UPD_CLK BIT(21)
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#define SDMMC_CMD_INIT BIT(15)
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#define SDMMC_CMD_STOP BIT(14)
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#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMMC_CMD_SEND_STOP BIT(12)
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#define SDMMC_CMD_STRM_MODE BIT(11)
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#define SDMMC_CMD_DAT_WR BIT(10)
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#define SDMMC_CMD_DAT_EXP BIT(9)
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#define SDMMC_CMD_RESP_CRC BIT(8)
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#define SDMMC_CMD_RESP_LONG BIT(7)
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#define SDMMC_CMD_RESP_EXP BIT(6)
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#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
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/* Status register defines */
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FF)
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#define SDMMC_FIFO_SZ 32
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/* Internal DMAC interrupt defines */
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#define SDMMC_IDMAC_INT_AI BIT(9)
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#define SDMMC_IDMAC_INT_NI BIT(8)
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#define SDMMC_IDMAC_INT_CES BIT(5)
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#define SDMMC_IDMAC_INT_DU BIT(4)
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#define SDMMC_IDMAC_INT_FBE BIT(2)
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#define SDMMC_IDMAC_INT_RI BIT(1)
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#define SDMMC_IDMAC_INT_TI BIT(0)
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/* Internal DMAC bus mode bits */
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#define SDMMC_IDMAC_ENABLE BIT(7)
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#define SDMMC_IDMAC_FB BIT(1)
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#define SDMMC_IDMAC_SWRESET BIT(0)
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/* Register access macros */
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#define mci_readl(dev, reg) \
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__raw_readl(dev->regs + SDMMC_##reg)
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#define mci_writel(dev, reg, value) \
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__raw_writel((value), dev->regs + SDMMC_##reg)
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/* 16-bit FIFO access macros */
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#define mci_readw(dev, reg) \
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__raw_readw(dev->regs + SDMMC_##reg)
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#define mci_writew(dev, reg, value) \
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__raw_writew((value), dev->regs + SDMMC_##reg)
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/* 64-bit FIFO access macros */
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#ifdef readq
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#define mci_readq(dev, reg) \
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__raw_readq(dev->regs + SDMMC_##reg)
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#define mci_writeq(dev, reg, value) \
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__raw_writeq((value), dev->regs + SDMMC_##reg)
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#else
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/*
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* Dummy readq implementation for architectures that don't define it.
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*
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* We would assume that none of these architectures would configure
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* the IP block with a 64bit FIFO width, so this code will never be
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* executed on those machines. Defining these macros here keeps the
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* rest of the code free from ifdefs.
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*/
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#define mci_readq(dev, reg) \
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(*(volatile u64 __force *)(dev->regs + SDMMC_##reg))
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#define mci_writeq(dev, reg, value) \
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(*(volatile u64 __force *)(dev->regs + SDMMC_##reg) = value)
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#endif
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#endif /* _DW_MMC_H_ */
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217
include/linux/mmc/dw_mmc.h
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217
include/linux/mmc/dw_mmc.h
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@ -0,0 +1,217 @@
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/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _LINUX_MMC_DW_MMC_H_
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#define _LINUX_MMC_DW_MMC_H_
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#define MAX_MCI_SLOTS 2
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enum dw_mci_state {
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STATE_IDLE = 0,
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STATE_SENDING_CMD,
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STATE_SENDING_DATA,
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STATE_DATA_BUSY,
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STATE_SENDING_STOP,
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STATE_DATA_ERROR,
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};
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enum {
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EVENT_CMD_COMPLETE = 0,
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EVENT_XFER_COMPLETE,
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EVENT_DATA_COMPLETE,
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EVENT_DATA_ERROR,
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EVENT_XFER_ERROR
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};
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struct mmc_data;
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/**
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* struct dw_mci - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @regs: Pointer to MMIO registers.
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* @sg: Scatterlist entry currently being processed by PIO code, if any.
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* @pio_offset: Offset into the current scatterlist entry.
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* @cur_slot: The slot which is currently using the controller.
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* @mrq: The request currently being processed on @cur_slot,
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* or NULL if the controller is idle.
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @use_dma: Whether DMA channel is initialized or not.
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* @sg_dma: Bus address of DMA buffer.
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* @sg_cpu: Virtual address of DMA buffer.
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* @dma_ops: Pointer to platform-specific DMA callbacks.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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* command. Only valid when EVENT_CMD_COMPLETE is pending.
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* @data_status: Snapshot of SR taken upon completion of the current
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* data transfer. Only valid when EVENT_DATA_COMPLETE or
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* EVENT_DATA_ERROR is pending.
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is
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* to be sent.
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* @dir_status: Direction of current transfer.
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* @tasklet: Tasklet running the request state machine.
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* @card_tasklet: Tasklet handling card detect.
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* @pending_events: Bitmask of events flagged by the interrupt handler
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* to be processed by the tasklet.
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* @completed_events: Bitmask of events which the state machine has
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* processed.
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* @state: Tasklet state.
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* @queue: List of slots waiting for access to the controller.
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
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* rate and timeout calculations.
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* @current_speed: Configured rate of the controller.
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* @num_slots: Number of slots available.
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* @pdev: Platform device associated with the MMC controller.
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* @pdata: Platform data associated with the MMC controller.
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* @slot: Slots sharing this MMC controller.
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* @data_shift: log2 of FIFO item size.
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* @push_data: Pointer to FIFO push function.
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* @pull_data: Pointer to FIFO pull function.
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* @quirks: Set of quirks that apply to specific versions of the IP.
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*
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* Locking
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* =======
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*
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* @lock is a softirq-safe spinlock protecting @queue as well as
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* @cur_slot, @mrq and @state. These must always be updated
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* at the same time while holding @lock.
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*
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* The @mrq field of struct dw_mci_slot is also protected by @lock,
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* and must always be written at the same time as the slot is added to
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* @queue.
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*
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* @pending_events and @completed_events are accessed using atomic bit
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* operations, so they don't need any locking.
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*
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* None of the fields touched by the interrupt handler need any
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
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* interrupts must be disabled and @data_status updated with a
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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* CMDRDY interupt must be disabled and @cmd_status updated with a
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
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* bytes_xfered field of @data must be written. This is ensured by
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* using barriers.
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*/
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struct dw_mci {
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spinlock_t lock;
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void __iomem *regs;
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struct scatterlist *sg;
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unsigned int pio_offset;
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struct dw_mci_slot *cur_slot;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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/* DMA interface members*/
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int use_dma;
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dma_addr_t sg_dma;
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void *sg_cpu;
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struct dw_mci_dma_ops *dma_ops;
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#ifdef CONFIG_MMC_DW_IDMAC
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unsigned int ring_size;
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#else
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struct dw_mci_dma_data *dma_data;
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#endif
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u32 cmd_status;
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u32 data_status;
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u32 stop_cmdr;
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u32 dir_status;
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struct tasklet_struct tasklet;
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struct tasklet_struct card_tasklet;
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unsigned long pending_events;
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unsigned long completed_events;
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enum dw_mci_state state;
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struct list_head queue;
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u32 bus_hz;
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u32 current_speed;
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u32 num_slots;
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struct platform_device *pdev;
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struct dw_mci_board *pdata;
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struct dw_mci_slot *slot[MAX_MCI_SLOTS];
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/* FIFO push and pull */
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int data_shift;
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void (*push_data)(struct dw_mci *host, void *buf, int cnt);
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void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
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/* Workaround flags */
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u32 quirks;
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};
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/* DMA ops for Internal/External DMAC interface */
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struct dw_mci_dma_ops {
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/* DMA Ops */
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int (*init)(struct dw_mci *host);
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void (*start)(struct dw_mci *host, unsigned int sg_len);
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void (*complete)(struct dw_mci *host);
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void (*stop)(struct dw_mci *host);
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void (*cleanup)(struct dw_mci *host);
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void (*exit)(struct dw_mci *host);
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};
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/* IP Quirks/flags. */
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/* No special quirks or flags to cater for */
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#define DW_MCI_QUIRK_NONE 0
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/* DTO fix for command transmission with IDMAC configured */
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#define DW_MCI_QUIRK_IDMAC_DTO 1
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/* delay needed between retries on some 2.11a implementations */
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#define DW_MCI_QUIRK_RETRY_DELAY 2
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/* High Speed Capable - Supports HS cards (upto 50MHz) */
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#define DW_MCI_QUIRK_HIGHSPEED 4
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struct dma_pdata;
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struct block_settings {
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unsigned short max_segs; /* see blk_queue_max_segments */
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unsigned int max_blk_size; /* maximum size of one mmc block */
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unsigned int max_blk_count; /* maximum number of blocks in one req*/
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unsigned int max_req_size; /* maximum number of bytes in one req*/
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unsigned int max_seg_size; /* see blk_queue_max_segment_size */
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};
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/* Board platform data */
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struct dw_mci_board {
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u32 num_slots;
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u32 quirks; /* Workaround / Quirk flags */
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unsigned int bus_hz; /* Bus speed */
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/* delay in mS before detecting cards after interrupt */
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u32 detect_delay_ms;
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int (*init)(u32 slot_id, irq_handler_t , void *);
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int (*get_ro)(u32 slot_id);
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int (*get_cd)(u32 slot_id);
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int (*get_ocr)(u32 slot_id);
|
||||
int (*get_bus_wd)(u32 slot_id);
|
||||
/*
|
||||
* Enable power to selected slot and set voltage to desired level.
|
||||
* Voltage levels are specified using MMC_VDD_xxx defines defined
|
||||
* in linux/mmc/host.h file.
|
||||
*/
|
||||
void (*setpower)(u32 slot_id, u32 volt);
|
||||
void (*exit)(u32 slot_id);
|
||||
void (*select_slot)(u32 slot_id);
|
||||
|
||||
struct dw_mci_dma_ops *dma_ops;
|
||||
struct dma_pdata *data;
|
||||
struct block_settings *blk_settings;
|
||||
};
|
||||
|
||||
#endif /* _LINUX_MMC_DW_MMC_H_ */
|
Loading…
Reference in New Issue
Block a user