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i40e/i40evf: AdminQ API update for new FW
Add set_pf_context, replace set_phy_reset with set_phy_debug, add nvm_config_read/write, remove nvm_read/write_reg_se and add some PHY types. With these changes we bump the API version to 1.2. Change-ID: I4dc3aec175c2316f66fc9b726b3f7d594699d84e Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Shannon Nelson
Jeff Kirsher
parent
5d29896a81
commit
f94234ee6d
@ -34,7 +34,7 @@
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*/
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#define I40E_FW_API_VERSION_MAJOR 0x0001
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#define I40E_FW_API_VERSION_MINOR 0x0001
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#define I40E_FW_API_VERSION_MINOR 0x0002
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struct i40e_aq_desc {
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__le16 flags;
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@ -123,6 +123,7 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_get_version = 0x0001,
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i40e_aqc_opc_driver_version = 0x0002,
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i40e_aqc_opc_queue_shutdown = 0x0003,
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i40e_aqc_opc_set_pf_context = 0x0004,
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/* resource ownership */
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i40e_aqc_opc_request_resource = 0x0008,
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@ -222,13 +223,15 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_get_partner_advt = 0x0616,
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i40e_aqc_opc_set_lb_modes = 0x0618,
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i40e_aqc_opc_get_phy_wol_caps = 0x0621,
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i40e_aqc_opc_set_phy_reset = 0x0622,
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i40e_aqc_opc_set_phy_debug = 0x0622,
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i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
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/* NVM commands */
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i40e_aqc_opc_nvm_read = 0x0701,
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i40e_aqc_opc_nvm_erase = 0x0702,
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i40e_aqc_opc_nvm_update = 0x0703,
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i40e_aqc_opc_nvm_read = 0x0701,
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i40e_aqc_opc_nvm_erase = 0x0702,
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i40e_aqc_opc_nvm_update = 0x0703,
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i40e_aqc_opc_nvm_config_read = 0x0704,
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i40e_aqc_opc_nvm_config_write = 0x0705,
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/* virtualization commands */
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i40e_aqc_opc_send_msg_to_pf = 0x0801,
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@ -270,8 +273,6 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_debug_set_mode = 0xFF01,
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i40e_aqc_opc_debug_read_reg = 0xFF03,
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i40e_aqc_opc_debug_write_reg = 0xFF04,
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i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
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i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
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i40e_aqc_opc_debug_modify_reg = 0xFF07,
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i40e_aqc_opc_debug_dump_internals = 0xFF08,
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i40e_aqc_opc_debug_modify_internals = 0xFF09,
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@ -339,6 +340,14 @@ struct i40e_aqc_queue_shutdown {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
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/* Set PF context (0x0004, direct) */
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struct i40e_aqc_set_pf_context {
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u8 pf_id;
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u8 reserved[15];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
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/* Request resource ownership (direct 0x0008)
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* Release resource ownership (direct 0x0009)
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*/
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@ -1404,11 +1413,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
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struct i40e_aqc_configure_switching_comp_ets_data {
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u8 reserved[4];
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u8 tc_valid_bits;
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u8 reserved1;
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u8 seepage;
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#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
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u8 tc_strict_priority_flags;
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u8 reserved2[17];
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u8 reserved1[17];
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u8 tc_bw_share_credits[8];
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u8 reserved3[96];
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u8 reserved2[96];
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};
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/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
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@ -1525,6 +1535,8 @@ enum i40e_aq_phy_type {
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I40E_PHY_TYPE_XLPPI = 0x9,
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I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
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I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
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I40E_PHY_TYPE_10GBASE_AOC = 0xC,
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I40E_PHY_TYPE_40GBASE_AOC = 0xD,
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I40E_PHY_TYPE_100BASE_TX = 0x11,
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I40E_PHY_TYPE_1000BASE_T = 0x12,
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I40E_PHY_TYPE_10GBASE_T = 0x13,
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@ -1535,7 +1547,10 @@ enum i40e_aq_phy_type {
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I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
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I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
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I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
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I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
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I40E_PHY_TYPE_1000BASE_SX = 0x1B,
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I40E_PHY_TYPE_1000BASE_LX = 0x1C,
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I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
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I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
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I40E_PHY_TYPE_MAX
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};
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@ -1679,6 +1694,7 @@ struct i40e_aqc_get_link_status {
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#define I40E_AQ_LINK_TX_ACTIVE 0x00
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#define I40E_AQ_LINK_TX_DRAINED 0x01
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#define I40E_AQ_LINK_TX_FLUSHED 0x03
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#define I40E_AQ_LINK_FORCED_40G 0x10
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u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
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__le16 max_frame_size;
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u8 config;
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@ -1730,14 +1746,21 @@ struct i40e_aqc_set_lb_mode {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
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/* Set PHY Reset command (0x0622) */
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struct i40e_aqc_set_phy_reset {
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u8 reset_flags;
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#define I40E_AQ_PHY_RESET_REQUEST 0x02
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/* Set PHY Debug command (0x0622) */
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struct i40e_aqc_set_phy_debug {
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u8 command_flags;
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#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
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I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
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#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
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u8 reserved[15];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
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enum i40e_aq_phy_reg_type {
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I40E_AQC_PHY_REG_INTERNAL = 0x1,
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@ -1762,6 +1785,47 @@ struct i40e_aqc_nvm_update {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
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/* NVM Config Read (indirect 0x0704) */
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struct i40e_aqc_nvm_config_read {
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__le16 cmd_flags;
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#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
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#define ANVM_READ_SINGLE_FEATURE 0
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#define ANVM_READ_MULTIPLE_FEATURES 1
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__le16 element_count;
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__le16 element_id; /* Feature/field ID */
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u8 reserved[2];
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__le32 address_high;
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__le32 address_low;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
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/* NVM Config Write (indirect 0x0705) */
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struct i40e_aqc_nvm_config_write {
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__le16 cmd_flags;
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__le16 element_count;
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u8 reserved[4];
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__le32 address_high;
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__le32 address_low;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
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struct i40e_aqc_nvm_config_data_feature {
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__le16 feature_id;
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__le16 instance_id;
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__le16 feature_options;
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__le16 feature_selection;
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};
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struct i40e_aqc_nvm_config_data_immediate_field {
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#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
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__le16 field_id;
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__le16 instance_id;
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__le16 field_options;
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__le16 field_value;
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};
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/* Send to PF command (indirect 0x0801) id is only used by PF
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* Send to VF command (indirect 0x0802) id is only used by PF
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* Send to Peer PF command (indirect 0x0803)
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@ -70,7 +70,7 @@ i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
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u16 *fw_major_version, u16 *fw_minor_version,
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u16 *api_major_version, u16 *api_minor_version,
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struct i40e_asq_cmd_details *cmd_details);
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i40e_status i40e_aq_set_phy_reset(struct i40e_hw *hw,
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i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
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struct i40e_asq_cmd_details *cmd_details);
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i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
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struct i40e_asq_cmd_details *cmd_details);
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@ -34,7 +34,7 @@
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*/
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#define I40E_FW_API_VERSION_MAJOR 0x0001
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#define I40E_FW_API_VERSION_MINOR 0x0001
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#define I40E_FW_API_VERSION_MINOR 0x0002
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#define I40E_FW_API_VERSION_A0_MINOR 0x0000
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struct i40e_aq_desc {
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@ -124,6 +124,7 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_get_version = 0x0001,
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i40e_aqc_opc_driver_version = 0x0002,
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i40e_aqc_opc_queue_shutdown = 0x0003,
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i40e_aqc_opc_set_pf_context = 0x0004,
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/* resource ownership */
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i40e_aqc_opc_request_resource = 0x0008,
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@ -223,13 +224,15 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_get_partner_advt = 0x0616,
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i40e_aqc_opc_set_lb_modes = 0x0618,
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i40e_aqc_opc_get_phy_wol_caps = 0x0621,
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i40e_aqc_opc_set_phy_reset = 0x0622,
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i40e_aqc_opc_set_phy_debug = 0x0622,
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i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
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/* NVM commands */
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i40e_aqc_opc_nvm_read = 0x0701,
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i40e_aqc_opc_nvm_erase = 0x0702,
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i40e_aqc_opc_nvm_update = 0x0703,
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i40e_aqc_opc_nvm_read = 0x0701,
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i40e_aqc_opc_nvm_erase = 0x0702,
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i40e_aqc_opc_nvm_update = 0x0703,
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i40e_aqc_opc_nvm_config_read = 0x0704,
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i40e_aqc_opc_nvm_config_write = 0x0705,
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/* virtualization commands */
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i40e_aqc_opc_send_msg_to_pf = 0x0801,
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@ -271,8 +274,6 @@ enum i40e_admin_queue_opc {
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i40e_aqc_opc_debug_set_mode = 0xFF01,
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i40e_aqc_opc_debug_read_reg = 0xFF03,
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i40e_aqc_opc_debug_write_reg = 0xFF04,
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i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
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i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
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i40e_aqc_opc_debug_modify_reg = 0xFF07,
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i40e_aqc_opc_debug_dump_internals = 0xFF08,
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i40e_aqc_opc_debug_modify_internals = 0xFF09,
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@ -340,6 +341,14 @@ struct i40e_aqc_queue_shutdown {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
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/* Set PF context (0x0004, direct) */
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struct i40e_aqc_set_pf_context {
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u8 pf_id;
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u8 reserved[15];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
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/* Request resource ownership (direct 0x0008)
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* Release resource ownership (direct 0x0009)
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*/
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@ -1408,11 +1417,12 @@ I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
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struct i40e_aqc_configure_switching_comp_ets_data {
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u8 reserved[4];
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u8 tc_valid_bits;
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u8 reserved1;
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u8 seepage;
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#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
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u8 tc_strict_priority_flags;
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u8 reserved2[17];
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u8 reserved1[17];
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u8 tc_bw_share_credits[8];
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u8 reserved3[96];
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u8 reserved2[96];
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};
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/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
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@ -1529,6 +1539,8 @@ enum i40e_aq_phy_type {
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I40E_PHY_TYPE_XLPPI = 0x9,
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I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
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I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
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I40E_PHY_TYPE_10GBASE_AOC = 0xC,
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I40E_PHY_TYPE_40GBASE_AOC = 0xD,
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I40E_PHY_TYPE_100BASE_TX = 0x11,
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I40E_PHY_TYPE_1000BASE_T = 0x12,
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I40E_PHY_TYPE_10GBASE_T = 0x13,
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@ -1539,7 +1551,10 @@ enum i40e_aq_phy_type {
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I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
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I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
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I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
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I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
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I40E_PHY_TYPE_1000BASE_SX = 0x1B,
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I40E_PHY_TYPE_1000BASE_LX = 0x1C,
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I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
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I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
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I40E_PHY_TYPE_MAX
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};
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@ -1683,6 +1698,7 @@ struct i40e_aqc_get_link_status {
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#define I40E_AQ_LINK_TX_ACTIVE 0x00
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#define I40E_AQ_LINK_TX_DRAINED 0x01
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#define I40E_AQ_LINK_TX_FLUSHED 0x03
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#define I40E_AQ_LINK_FORCED_40G 0x10
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u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
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__le16 max_frame_size;
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u8 config;
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@ -1734,14 +1750,21 @@ struct i40e_aqc_set_lb_mode {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
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/* Set PHY Reset command (0x0622) */
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struct i40e_aqc_set_phy_reset {
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u8 reset_flags;
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#define I40E_AQ_PHY_RESET_REQUEST 0x02
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/* Set PHY Debug command (0x0622) */
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struct i40e_aqc_set_phy_debug {
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u8 command_flags;
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#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
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I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
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#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
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#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
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u8 reserved[15];
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
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I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
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enum i40e_aq_phy_reg_type {
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I40E_AQC_PHY_REG_INTERNAL = 0x1,
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@ -1766,6 +1789,47 @@ struct i40e_aqc_nvm_update {
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
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/* NVM Config Read (indirect 0x0704) */
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struct i40e_aqc_nvm_config_read {
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__le16 cmd_flags;
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#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
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#define ANVM_READ_SINGLE_FEATURE 0
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#define ANVM_READ_MULTIPLE_FEATURES 1
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__le16 element_count;
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__le16 element_id; /* Feature/field ID */
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u8 reserved[2];
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__le32 address_high;
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__le32 address_low;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
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/* NVM Config Write (indirect 0x0705) */
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struct i40e_aqc_nvm_config_write {
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__le16 cmd_flags;
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__le16 element_count;
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u8 reserved[4];
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__le32 address_high;
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__le32 address_low;
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};
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I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
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struct i40e_aqc_nvm_config_data_feature {
|
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__le16 feature_id;
|
||||
__le16 instance_id;
|
||||
__le16 feature_options;
|
||||
__le16 feature_selection;
|
||||
};
|
||||
|
||||
struct i40e_aqc_nvm_config_data_immediate_field {
|
||||
#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2
|
||||
__le16 field_id;
|
||||
__le16 instance_id;
|
||||
__le16 field_options;
|
||||
__le16 field_value;
|
||||
};
|
||||
|
||||
/* Send to PF command (indirect 0x0801) id is only used by PF
|
||||
* Send to VF command (indirect 0x0802) id is only used by PF
|
||||
* Send to Peer PF command (indirect 0x0803)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user