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perf vendor events intel: Update knightslanding events to v16
Update knightslanding from v10 to v16 adding the changes from:6c1f169f6eb22ca587ece685286f08Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Edward Baker <edward.baker@intel.com> Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20231026003149.3287633-5-irogers@google.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Ian Rogers
Namhyung Kim
parent
20e6a51f61
commit
f9418b524d
@ -6,13 +6,19 @@
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"SampleAfterValue": "200003"
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},
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{
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"BriefDescription": "Counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of core cycles the fetch stalled for all icache misses.",
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"BriefDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
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"EventCode": "0x86",
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"EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES",
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"PublicDescription": "This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses.",
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"SampleAfterValue": "200003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of L2HWP allocated into XQ GP",
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"EventCode": "0x3E",
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"EventName": "L2_PREFETCHER.ALLOC_XQ",
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"SampleAfterValue": "100007",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of L2 cache misses",
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"EventCode": "0x2E",
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@ -28,7 +34,7 @@
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"UMask": "0x4f"
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},
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{
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"BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically exlcudes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
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"BriefDescription": "Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times",
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"EventCode": "0x30",
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"EventName": "L2_REQUESTS_REJECT.ALL",
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"SampleAfterValue": "200003"
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@ -50,11 +56,12 @@
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state",
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"BriefDescription": "Counts the loads retired that get the data from the other core in the same tile in M state (Precise Event)",
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"Data_LA": "1",
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"EventCode": "0x04",
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"EventName": "MEM_UOPS_RETIRED.HITM",
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"PEBS": "1",
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"PublicDescription": "This event counts the number of load micro-ops retired that got data from another core's cache. (Precise Event).",
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"SampleAfterValue": "200003",
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"UMask": "0x20"
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},
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@ -67,20 +74,22 @@
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2",
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"BriefDescription": "Counts the number of load micro-ops retired that hit in the L2 (Precise Event)",
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"Data_LA": "1",
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"EventCode": "0x04",
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"EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS",
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"PEBS": "1",
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"PublicDescription": "This event counts the number of load micro-uops retired that hit in the L2 (Precise Event)",
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"SampleAfterValue": "200003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2",
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"BriefDescription": "Counts the number of load micro-ops retired that miss in the L2 (Precise Event)",
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"Data_LA": "1",
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"EventCode": "0x04",
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"EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS",
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"PEBS": "1",
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"PublicDescription": "This event counts the number of load micro-ops retired that miss in the L2 (Precise Event)",
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"SampleAfterValue": "100007",
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"UMask": "0x4"
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},
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@ -620,6 +629,15 @@
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Accounts for responses which miss its own tile's L2.",
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"EventCode": "0xB7",
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"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x18001981F8",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0.",
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"EventCode": "0xB7",
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@ -1664,15 +1682,6 @@
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L2 data RFO prefetches (includes PREFETCHW instruction) that provides no supplier details",
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"EventCode": "0xB7",
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"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x0000020020",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts Software Prefetches that accounts for any response",
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"EventCode": "0xB7",
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@ -8,18 +8,18 @@
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of vector SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
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"BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.PACKED_SIMD",
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"PublicDescription": "This event counts the number of packed vector SSE, AVX, AVX2, and AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
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"PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired. More specifically, it counts scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
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"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.SCALAR_SIMD",
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"PublicDescription": "This event counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops retired (floating point, integer and store) except for loads (memory-to-register mov-type micro ops), division, sqrt.",
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"PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x20"
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}
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@ -1,13 +1,13 @@
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[
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{
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"BriefDescription": "Counts the number of branch instructions retired",
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"BriefDescription": "Counts the number of branch instructions retired (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"SampleAfterValue": "200003"
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},
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{
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"BriefDescription": "Counts the number of near CALL branch instructions retired.",
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"BriefDescription": "Counts the number of near CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.CALL",
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"PEBS": "1",
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@ -15,7 +15,7 @@
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"UMask": "0xf9"
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},
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{
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"BriefDescription": "Counts the number of far branch instructions retired.",
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"BriefDescription": "Counts the number of far branch instructions retired. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.FAR_BRANCH",
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"PEBS": "1",
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@ -23,7 +23,7 @@
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"UMask": "0xbf"
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},
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{
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"BriefDescription": "Counts the number of near indirect CALL branch instructions retired.",
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"BriefDescription": "Counts the number of near indirect CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.IND_CALL",
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"PEBS": "1",
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@ -31,7 +31,7 @@
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"UMask": "0xfb"
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},
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{
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"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps.",
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"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.JCC",
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"PEBS": "1",
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@ -39,7 +39,7 @@
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"UMask": "0x7e"
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},
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{
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"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP.",
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"BriefDescription": "Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
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"PEBS": "1",
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@ -47,7 +47,7 @@
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"UMask": "0xeb"
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},
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{
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"BriefDescription": "Counts the number of near relative CALL branch instructions retired.",
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"BriefDescription": "Counts the number of near relative CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.REL_CALL",
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"PEBS": "1",
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@ -55,7 +55,7 @@
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"UMask": "0xfd"
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},
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{
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"BriefDescription": "Counts the number of near RET branch instructions retired.",
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"BriefDescription": "Counts the number of near RET branch instructions retired. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.RETURN",
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"PEBS": "1",
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@ -63,7 +63,7 @@
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"UMask": "0xf7"
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},
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{
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"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken.",
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"BriefDescription": "Counts the number of branch instructions retired that were conditional jumps and predicted taken. (Precise Event)",
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"EventCode": "0xC4",
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"EventName": "BR_INST_RETIRED.TAKEN_JCC",
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"PEBS": "1",
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@ -71,14 +71,14 @@
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"UMask": "0xfe"
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},
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{
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"BriefDescription": "Counts the number of mispredicted branch instructions retired",
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"BriefDescription": "Counts the number of mispredicted branch instructions retired (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
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"PEBS": "1",
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"SampleAfterValue": "200003"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired.",
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"BriefDescription": "Counts the number of mispredicted near CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.CALL",
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"PEBS": "1",
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@ -86,7 +86,7 @@
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"UMask": "0xf9"
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},
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{
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"BriefDescription": "Counts the number of mispredicted far branch instructions retired.",
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"BriefDescription": "Counts the number of mispredicted far branch instructions retired. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.FAR_BRANCH",
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"PEBS": "1",
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@ -94,7 +94,7 @@
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"UMask": "0xbf"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.",
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"BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.IND_CALL",
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"PEBS": "1",
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@ -102,7 +102,7 @@
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"UMask": "0xfb"
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},
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{
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps.",
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.JCC",
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"PEBS": "1",
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@ -110,7 +110,7 @@
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"UMask": "0x7e"
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},
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{
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP.",
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
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"PEBS": "1",
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@ -118,7 +118,7 @@
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"UMask": "0xeb"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired.",
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"BriefDescription": "Counts the number of mispredicted near relative CALL branch instructions retired. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.REL_CALL",
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"PEBS": "1",
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@ -126,7 +126,7 @@
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"UMask": "0xfd"
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},
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{
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"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.",
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"BriefDescription": "Counts the number of mispredicted near RET branch instructions retired. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.RETURN",
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"PEBS": "1",
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@ -134,7 +134,7 @@
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"UMask": "0xf7"
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},
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{
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken.",
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"BriefDescription": "Counts the number of mispredicted branch instructions retired that were conditional jumps and predicted taken. (Precise Event)",
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"EventCode": "0xC5",
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"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
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"PEBS": "1",
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@ -189,7 +189,14 @@
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"SampleAfterValue": "2000003"
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},
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{
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"BriefDescription": "Counts all nukes",
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"BriefDescription": "Counts the number of instructions retired (Precise Event)",
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"EventCode": "0xC0",
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"EventName": "INST_RETIRED.ANY_PS",
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"PEBS": "2",
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"SampleAfterValue": "2000003"
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},
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{
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"BriefDescription": "Counts all machine clears",
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"EventCode": "0xC3",
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"EventName": "MACHINE_CLEARS.ALL",
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"SampleAfterValue": "200003",
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@ -261,20 +268,22 @@
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store",
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"BriefDescription": "Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store (Precise Event)",
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"Data_LA": "1",
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"EventCode": "0x03",
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"EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD",
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"PEBS": "1",
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"PublicDescription": "This event counts the number of retired loads that were prohibited from receiving forwarded data from a previous store because of address mismatch.",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once.",
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"BriefDescription": "Counts the number of occurrences a retired load was pushed into the rehab queue because it sees a cache line split. Each split should be counted only once. (Precise Event)",
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"Data_LA": "1",
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"EventCode": "0x03",
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"EventName": "RECYCLEQ.LD_SPLITS",
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"PEBS": "1",
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"PublicDescription": "This event counts the number of retired loads which was pushed into the recycled queue that experienced cache line boundary splits (Precise event). Not that each split should be counted only once.",
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"SampleAfterValue": "200003",
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"UMask": "0x8"
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},
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@ -286,7 +295,7 @@
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full",
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"BriefDescription": "Counts the store micro-ops retired that were pushed in the rehab queue because the store address buffer is full",
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"EventCode": "0x03",
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"EventName": "RECYCLEQ.STA_FULL",
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"SampleAfterValue": "200003",
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@ -301,7 +310,7 @@
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the total number of core cycles the Alloc pipeline is stalled when any one of the reservation stations is full.",
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"BriefDescription": "Counts the total number of core cycles allocation pipeline is stalled when any one of the reservation stations is full.",
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"EventCode": "0xCB",
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"EventName": "RS_FULL_STALL.ALL",
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"SampleAfterValue": "200003",
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@ -2558,7 +2558,7 @@
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"Unit": "CHA"
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},
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{
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"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
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"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
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"EventCode": "0x2A",
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"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0",
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"PerPkg": "1",
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@ -2566,7 +2566,7 @@
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"Unit": "CHA"
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},
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{
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"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0",
|
||||
"PerPkg": "1",
|
||||
@ -2574,7 +2574,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI",
|
||||
"PerPkg": "1",
|
||||
@ -2582,7 +2582,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0",
|
||||
"PerPkg": "1",
|
||||
@ -2590,7 +2590,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0",
|
||||
"PerPkg": "1",
|
||||
@ -2598,7 +2598,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0",
|
||||
"PerPkg": "1",
|
||||
@ -2606,7 +2606,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0",
|
||||
"PerPkg": "1",
|
||||
@ -2614,7 +2614,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2A",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI",
|
||||
"PerPkg": "1",
|
||||
@ -2622,7 +2622,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP",
|
||||
"PerPkg": "1",
|
||||
@ -2630,7 +2630,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0",
|
||||
"PerPkg": "1",
|
||||
@ -2638,7 +2638,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH",
|
||||
"PerPkg": "1",
|
||||
@ -2646,7 +2646,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM",
|
||||
"PerPkg": "1",
|
||||
@ -2654,7 +2654,7 @@
|
||||
"Unit": "CHA"
|
||||
},
|
||||
{
|
||||
"BriefDescription": "REQUESTQ'' includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
|
||||
"EventCode": "0x2B",
|
||||
"EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY",
|
||||
"PerPkg": "1",
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
[
|
||||
{
|
||||
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss",
|
||||
"BriefDescription": "Counts the number of load micro-ops retired that cause a DTLB miss (Precise Event)",
|
||||
"Data_LA": "1",
|
||||
"EventCode": "0x04",
|
||||
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
|
||||
|
||||
@ -19,7 +19,7 @@ GenuineIntel-6-6[AC],v1.21,icelakex,core
|
||||
GenuineIntel-6-3A,v24,ivybridge,core
|
||||
GenuineIntel-6-3E,v24,ivytown,core
|
||||
GenuineIntel-6-2D,v24,jaketown,core
|
||||
GenuineIntel-6-(57|85),v10,knightslanding,core
|
||||
GenuineIntel-6-(57|85),v16,knightslanding,core
|
||||
GenuineIntel-6-BD,v1.00,lunarlake,core
|
||||
GenuineIntel-6-A[AC],v1.04,meteorlake,core
|
||||
GenuineIntel-6-1[AEF],v4,nehalemep,core
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user