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dt-bindings: net: sparx5: Add sparx5-switch bindings
Document the Sparx5 switch device driver bindings Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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Steen Hegelund
David S. Miller
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Sparx5 Ethernet switch controller
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maintainers:
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- Steen Hegelund <steen.hegelund@microchip.com>
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- Lars Povlsen <lars.povlsen@microchip.com>
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description: |
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The SparX-5 Enterprise Ethernet switch family provides a rich set of
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Enterprise switching features such as advanced TCAM-based VLAN and
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QoS processing enabling delivery of differentiated services, and
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security through TCAM-based frame processing using versatile content
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aware processor (VCAP).
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IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
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with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
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IPv6 (S,G) multicast groups.
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L3 security features include source guard and reverse path
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forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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IP tunnels (IP over GRE/IP).
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The SparX-5 switch family targets managed Layer 2 and Layer 3
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equipment in SMB, SME, and Enterprise where high port count
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1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
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properties:
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$nodename:
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pattern: "^switch@[0-9a-f]+$"
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compatible:
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const: microchip,sparx5-switch
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reg:
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items:
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- description: cpu target
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- description: devices target
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- description: general control block target
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reg-names:
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items:
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- const: cpu
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- const: devices
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- const: gcb
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interrupts:
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minItems: 1
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items:
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- description: register based extraction
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- description: frame dma based extraction
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interrupt-names:
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minItems: 1
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items:
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- const: xtr
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- const: fdma
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resets:
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items:
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- description: Reset controller used for switch core reset (soft reset)
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reset-names:
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items:
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- const: switch
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mac-address: true
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ethernet-ports:
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type: object
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patternProperties:
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"^port@[0-9a-f]+$":
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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description: Switch port number
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phys:
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maxItems: 1
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description:
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phandle of a Ethernet SerDes PHY. This defines which SerDes
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instance will handle the Ethernet traffic.
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phy-mode:
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description:
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This specifies the interface used by the Ethernet SerDes towards
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the PHY or SFP.
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microchip,bandwidth:
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description: Specifies bandwidth in Mbit/s allocated to the port.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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maximum: 25000
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phy-handle:
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description:
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phandle of a Ethernet PHY. This is optional and if provided it
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points to the cuPHY used by the Ethernet SerDes.
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sfp:
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description:
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phandle of an SFP. This is optional and used when not specifying
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a cuPHY. It points to the SFP node that describes the SFP used by
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the Ethernet SerDes.
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managed: true
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microchip,sd-sgpio:
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description:
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Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
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This is optional, and only needed if the default used index is
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is not correct.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 383
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required:
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- reg
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- phys
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- phy-mode
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- microchip,bandwidth
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oneOf:
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- required:
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- phy-handle
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- required:
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- sfp
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- managed
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- resets
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- reset-names
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- ethernet-ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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switch: switch@600000000 {
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compatible = "microchip,sparx5-switch";
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reg = <0 0x401000>,
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<0x10004000 0x7fc000>,
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<0x11010000 0xaf0000>;
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reg-names = "cpu", "devices", "gcb";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "xtr";
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resets = <&reset 0>;
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reset-names = "switch";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0: port@0 {
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reg = <0>;
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microchip,bandwidth = <1000>;
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phys = <&serdes 13>;
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phy-handle = <&phy0>;
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phy-mode = "qsgmii";
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};
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/* ... */
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/* Then the 25G interfaces */
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port60: port@60 {
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reg = <60>;
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microchip,bandwidth = <25000>;
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phys = <&serdes 29>;
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phy-mode = "10gbase-r";
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sfp = <&sfp_eth60>;
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managed = "in-band-status";
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microchip,sd-sgpio = <365>;
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};
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port61: port@61 {
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reg = <61>;
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microchip,bandwidth = <25000>;
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phys = <&serdes 30>;
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phy-mode = "10gbase-r";
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sfp = <&sfp_eth61>;
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managed = "in-band-status";
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microchip,sd-sgpio = <369>;
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};
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port62: port@62 {
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reg = <62>;
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microchip,bandwidth = <25000>;
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phys = <&serdes 31>;
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phy-mode = "10gbase-r";
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sfp = <&sfp_eth62>;
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managed = "in-band-status";
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microchip,sd-sgpio = <373>;
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};
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port63: port@63 {
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reg = <63>;
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microchip,bandwidth = <25000>;
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phys = <&serdes 32>;
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phy-mode = "10gbase-r";
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sfp = <&sfp_eth63>;
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managed = "in-band-status";
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microchip,sd-sgpio = <377>;
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};
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/* Finally the Management interface */
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port64: port@64 {
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reg = <64>;
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microchip,bandwidth = <1000>;
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phys = <&serdes 0>;
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phy-handle = <&phy64>;
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phy-mode = "sgmii";
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mac-address = [ 00 00 00 01 02 03 ];
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};
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};
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};
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...
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# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
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