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[PATCH] m32r: support a synthesizable M32700 core

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This patch is for supporting a synthesizable M32700 core for the Mappi-II FPGA
board.

On the core, location of MFT (Multi-Function Timer) registers is slightly
different from the M32700 chip.

Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Hirokazu Takata 2006-12-08 02:35:55 -08:00 committed by Linus Torvalds
parent 8b03a632ef
commit f894cb5c93
1 changed files with 4 additions and 3 deletions
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7
include/asm-m32r/m32102.h
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@ -104,7 +104,8 @@
#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */ #define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */ #define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_M32104) #if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
|| defined(CONFIG_CHIP_M32104)
#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */ #define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */ #define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */ #define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
@ -117,7 +118,7 @@
#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */ #define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */ #define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */ #define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
#else /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ #else
#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */ #define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */ #define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */ #define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
@ -130,7 +131,7 @@
#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */ #define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */ #define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */ #define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
#endif /* not CONFIG_CHIP_M32700 && not CONFIG_CHIP_M32104 */ #endif
#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */ #define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */ #define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */