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drm/amd/display: Populate socclk entries for dcn3.02/3.03
[Why] Initialize socclk entries in bandwidth params for dcn302, dcn303. [How] Fetch the sockclk values from smu for the DPM levels and for the DPM levels where smu returns 0, previous level values are reported. Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
2e63f4064e
commit
f891ae71f3
drivers/gpu/drm/amd/display/dc
@ -190,6 +190,10 @@ void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
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&clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
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&num_levels);
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/* SOCCLK */
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dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
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&clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
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&num_levels);
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// DPREFCLK ???
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/* DISPCLK */
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@ -1399,10 +1399,13 @@ void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
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dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
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dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
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dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[0].dtbclk_mhz;
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if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
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dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
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else
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dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
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/* These clocks cannot come from bw_params, always fill from dcn3_02_soc[1] */
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/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
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/* FCLK, PHYCLK_D18, DSCCLK */
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dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
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dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[0].socclk_mhz;
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dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
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}
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/* re-init DML with updated bb */
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@ -1327,10 +1327,13 @@ void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
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dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
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dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
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dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[0].dtbclk_mhz;
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if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
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dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
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else
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dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
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/* These clocks cannot come from bw_params, always fill from dcn3_03_soc[1] */
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/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
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/* FCLK, PHYCLK_D18, DSCCLK */
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dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
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dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[0].socclk_mhz;
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dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
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}
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/* re-init DML with updated bb */
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