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drm/nv50/disp: move dp link training helpers into core

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2012-11-09 09:53:28 +10:00
parent 7ebb38b556
commit f7960736d0
6 changed files with 161 additions and 72 deletions
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1
drivers/gpu/drm/nouveau/Makefile
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@ -141,6 +141,7 @@ nouveau-y += core/engine/disp/dacnv50.o
nouveau-y += core/engine/disp/hdanvd0.o
nouveau-y += core/engine/disp/hdminvd0.o
nouveau-y += core/engine/disp/sornv50.o
nouveau-y += core/engine/disp/sornv94.o
nouveau-y += core/engine/disp/sornvd0.o
nouveau-y += core/engine/disp/vga.o
nouveau-y += core/engine/fifo/base.o

7
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
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@ -49,6 +49,13 @@ int nv50_dac_sense(struct nv50_disp_priv *, int, u32);
int nv50_sor_mthd(struct nouveau_object *, u32, void *, u32);
int nv50_sor_power(struct nv50_disp_priv *, int, u32);
int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
struct dcb_output *);
int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
struct dcb_output *);
int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
struct dcb_output *);
int nvd0_hda_eld(struct nv50_disp_priv *, int, u8 *, u32);
int nvd0_hdmi_ctrl(struct nv50_disp_priv *, int, int, u32);

3
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
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@ -84,6 +84,9 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.dp_train = nv94_sor_dp_train;
priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
INIT_LIST_HEAD(&priv->base.vblank.list);
spin_lock_init(&priv->base.vblank.lock);

3
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View File

@ -85,6 +85,9 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
priv->dac.power = nv50_dac_power;
priv->dac.sense = nv50_dac_sense;
priv->sor.power = nv50_sor_power;
priv->sor.dp_train = nv94_sor_dp_train;
priv->sor.dp_lnkctl = nv94_sor_dp_lnkctl;
priv->sor.dp_drvctl = nv94_sor_dp_drvctl;
INIT_LIST_HEAD(&priv->base.vblank.list);
spin_lock_init(&priv->base.vblank.lock);

132
drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c Normal file
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@ -0,0 +1,132 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/os.h>
#include <core/class.h>
#include <subdev/bios.h>
#include <subdev/bios/dcb.h>
#include <subdev/bios/dp.h>
#include <subdev/bios/init.h>
#include "nv50.h"
static inline u32
nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
{
static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
static const u8 nv94[] = { 16, 8, 0, 24 };
if (nv_device(priv)->chipset == 0xaf)
return nvaf[lane];
return nv94[lane];
}
int
nv94_sor_dp_train(struct nv50_disp_priv *priv, int or, int link,
u16 type, u16 mask, u32 data, struct dcb_output *info)
{
const u32 loff = (or * 0x800) + (link * 0x80);
const u32 patt = (data & NV94_DISP_SOR_DP_TRAIN_PATTERN);
nv_mask(priv, 0x61c10c + loff, 0x0f000000, patt << 24);
return 0;
}
int
nv94_sor_dp_lnkctl(struct nv50_disp_priv *priv, int or, int link, int head,
u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
{
struct nouveau_bios *bios = nouveau_bios(priv);
const u32 loff = (or * 0x800) + (link * 0x80);
const u32 soff = (or * 0x800);
u16 link_bw = (data & NV94_DISP_SOR_DP_LNKCTL_WIDTH) >> 8;
u8 link_nr = (data & NV94_DISP_SOR_DP_LNKCTL_COUNT);
u32 dpctrl = 0x00000000;
u32 clksor = 0x00000000;
u32 outp, lane = 0;
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
int i;
/* -> 10Khz units */
link_bw *= 2700;
outp = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &info);
if (outp && info.lnkcmp) {
struct nvbios_init init = {
.subdev = nv_subdev(priv),
.bios = bios,
.offset = 0x0000,
.outp = dcbo,
.crtc = head,
.execute = 1,
};
while (link_bw < nv_ro16(bios, info.lnkcmp))
info.lnkcmp += 4;
init.offset = nv_ro16(bios, info.lnkcmp + 2);
nvbios_exec(&init);
}
dpctrl |= ((1 << link_nr) - 1) << 16;
if (data & NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH)
dpctrl |= 0x00004000;
if (link_bw > 16200)
clksor |= 0x00040000;
for (i = 0; i < link_nr; i++)
lane |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3);
nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor);
nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
nv_mask(priv, 0x61c130 + loff, 0x0000000f, lane);
return 0;
}
int
nv94_sor_dp_drvctl(struct nv50_disp_priv *priv, int or, int link, int lane,
u16 type, u16 mask, u32 data, struct dcb_output *dcbo)
{
struct nouveau_bios *bios = nouveau_bios(priv);
const u32 loff = (or * 0x800) + (link * 0x80);
const u8 swing = (data & NV94_DISP_SOR_DP_DRVCTL_VS) >> 8;
const u8 preem = (data & NV94_DISP_SOR_DP_DRVCTL_PE);
u32 addr, shift = nv94_sor_dp_lane_map(priv, lane);
u8 ver, hdr, cnt, len;
struct nvbios_dpout outp;
struct nvbios_dpcfg ocfg;
addr = nvbios_dpout_match(bios, type, mask, &ver, &hdr, &cnt, &len, &outp);
if (!addr)
return -ENODEV;
addr = nvbios_dpcfg_match(bios, addr, 0, swing, preem, &ver, &hdr, &cnt, &len, &ocfg);
if (!addr)
return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
return 0;
}

87
drivers/gpu/drm/nouveau/nv50_sor.c
View File

@ -40,94 +40,37 @@
#include <subdev/timer.h>
static u32
nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
{
struct nouveau_drm *drm = nouveau_drm(dev);
static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
static const u8 nv50[] = { 16, 8, 0, 24 };
if (nv_device(drm->device)->chipset == 0xaf)
return nvaf[lane];
return nv50[lane];
}
static void
nv50_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
{
struct nouveau_device *device = nouveau_dev(dev);
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
nv_mask(device, NV50_SOR_DP_CTRL(or, link), 0x0f000000, pattern << 24);
struct nv50_display *disp = nv50_display(dev);
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 moff = (link << 2) | or;
nv_call(disp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern);
}
static void
nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
u8 lane, u8 swing, u8 preem)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_drm *drm = nouveau_drm(dev);
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
u32 mask = 0x000000ff << shift;
u8 *table, *entry, *config;
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
return;
}
config = entry + table[4];
while (config[0] != swing || config[1] != preem) {
config += table[5];
if (config >= entry + table[4] + entry[4] * table[5])
return;
}
nv_mask(device, NV50_SOR_DP_UNK118(or, link), mask, config[2] << shift);
nv_mask(device, NV50_SOR_DP_UNK120(or, link), mask, config[3] << shift);
nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000ff00, config[4] << 8);
struct nv50_display *disp = nv50_display(dev);
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 moff = (link << 2) | or;
const u32 data = (swing << 8) | preem;
nv_call(disp->core, NV94_DISP_SOR_DP_DRVCTL(lane) + moff, data);
}
static void
nv50_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
int link_nr, u32 link_bw, bool enhframe)
{
struct nouveau_device *device = nouveau_dev(dev);
struct nouveau_drm *drm = nouveau_drm(dev);
u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
u32 dpctrl = nv_rd32(device, NV50_SOR_DP_CTRL(or, link)) & ~0x001f4000;
u32 clksor = nv_rd32(device, 0x614300 + (or * 0x800)) & ~0x000c0000;
u8 *table, *entry, mask;
int i;
table = nouveau_dp_bios_data(dev, dcb, &entry);
if (!table || (table[0] != 0x20 && table[0] != 0x21)) {
NV_ERROR(drm, "PDISP: unsupported DP table for chipset\n");
return;
}
entry = ROMPTR(dev, entry[10]);
if (entry) {
while (link_bw < ROM16(entry[0]) * 10)
entry += 4;
nouveau_bios_run_init_table(dev, ROM16(entry[2]), dcb, crtc);
}
dpctrl |= ((1 << link_nr) - 1) << 16;
struct nv50_display *disp = nv50_display(dev);
const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
const u32 moff = (crtc << 3) | (link << 2) | or;
u32 data = ((link_bw / 27000) << 8) | link_nr;
if (enhframe)
dpctrl |= 0x00004000;
if (link_bw > 162000)
clksor |= 0x00040000;
nv_wr32(device, 0x614300 + (or * 0x800), clksor);
nv_wr32(device, NV50_SOR_DP_CTRL(or, link), dpctrl);
mask = 0;
for (i = 0; i < link_nr; i++)
mask |= 1 << (nv50_sor_dp_lane_map(dev, dcb, i) >> 3);
nv_mask(device, NV50_SOR_DP_UNK130(or, link), 0x0000000f, mask);
data |= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH;
nv_call(disp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data);
}
static void