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phy: ti: am654: update PCIe serdes config
Update PCIe serdes config to latest suggested for hardware. This fixes cases of failure to enumerate in Gen2 mode with some cards. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Link: https://lore.kernel.org/r/20200727194603.44636-4-nsekhar@ti.com [fix typo threshold] Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sekhar Nori
Vinod Koul
parent
b494bbb6c6
commit
f78c40aa86
@ -19,15 +19,38 @@
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#define CMU_R004 0x4
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#define CMU_R060 0x60
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#define CMU_R07C 0x7c
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#define CMU_R088 0x88
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#define CMU_R0D0 0xd0
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#define CMU_R0E8 0xe8
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#define LANE_R048 0x248
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#define LANE_R058 0x258
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#define LANE_R06c 0x26c
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#define LANE_R070 0x270
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#define LANE_R070 0x270
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#define LANE_R19C 0x39c
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#define COMLANE_R004 0xa04
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#define COMLANE_R138 0xb38
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#define VERSION_VAL 0x70
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#define COMLANE_R190 0xb90
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#define COMLANE_R194 0xb94
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#define COMRXEQ_R004 0x1404
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#define COMRXEQ_R008 0x1408
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#define COMRXEQ_R00C 0x140c
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#define COMRXEQ_R014 0x1414
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#define COMRXEQ_R018 0x1418
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#define COMRXEQ_R01C 0x141c
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#define COMRXEQ_R04C 0x144c
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#define COMRXEQ_R088 0x1488
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#define COMRXEQ_R094 0x1494
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#define COMRXEQ_R098 0x1498
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#define SERDES_CTRL 0x1fd0
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#define WIZ_LANEXCTL_STS 0x1fe0
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@ -81,8 +104,33 @@ static const struct regmap_config serdes_am654_regmap_config = {
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};
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enum serdes_am654_fields {
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/* CMU PLL Control */
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CMU_PLL_CTRL,
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LANE_PLL_CTRL_RXEQ_RXIDLE,
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/* CMU VCO bias current and VREG setting */
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AHB_PMA_CM_VCO_VBIAS_VREG,
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AHB_PMA_CM_VCO_BIAS_VREG,
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AHB_PMA_CM_SR,
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AHB_SSC_GEN_Z_O_20_13,
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/* AHB PMA Lane Configuration */
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AHB_PMA_LN_AGC_THSEL_VREGH,
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/* AGC and Signal detect threshold for Gen3 */
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AHB_PMA_LN_GEN3_AGC_SD_THSEL,
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AHB_PMA_LN_RX_SELR_GEN3,
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AHB_PMA_LN_TX_DRV,
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/* CMU Master Reset */
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CMU_MASTER_CDN,
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/* P2S ring buffer initial startup pointer difference */
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P2S_RBUF_PTR_DIFF,
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CONFIG_VERSION,
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/* Lane 1 Master Reset */
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@ -91,6 +139,42 @@ enum serdes_am654_fields {
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/* CMU OK Status */
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CMU_OK_I_0,
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/* Mid-speed initial calibration control */
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COMRXEQ_MS_INIT_CTRL_7_0,
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/* High-speed initial calibration control */
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COMRXEQ_HS_INIT_CAL_7_0,
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/* Mid-speed recalibration control */
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COMRXEQ_MS_RECAL_CTRL_7_0,
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/* High-speed recalibration control */
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COMRXEQ_HS_RECAL_CTRL_7_0,
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/* ATT configuration */
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COMRXEQ_CSR_ATT_CONFIG,
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/* Edge based boost adaptation window length */
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COMRXEQ_CSR_EBSTADAPT_WIN_LEN,
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/* COMRXEQ control 3 & 4 */
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COMRXEQ_CTRL_3_4,
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/* COMRXEQ control 14, 15 and 16*/
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COMRXEQ_CTRL_14_15_16,
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/* Threshold for errors in pattern data */
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COMRXEQ_CSR_DLEV_ERR_THRESH,
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/* COMRXEQ control 25 */
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COMRXEQ_CTRL_25,
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/* Mid-speed rate change calibration control */
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CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O,
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/* High-speed rate change calibration control */
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COMRXEQ_HS_RCHANGE_CTRL_7_0,
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/* Serdes reset */
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POR_EN,
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@ -112,10 +196,33 @@ enum serdes_am654_fields {
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};
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static const struct reg_field serdes_am654_reg_fields[] = {
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[CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 24),
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[CMU_PLL_CTRL] = REG_FIELD(CMU_R004, 8, 15),
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[AHB_PMA_CM_VCO_VBIAS_VREG] = REG_FIELD(CMU_R060, 8, 15),
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[CMU_MASTER_CDN] = REG_FIELD(CMU_R07C, 24, 31),
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[AHB_PMA_CM_VCO_BIAS_VREG] = REG_FIELD(CMU_R088, 24, 31),
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[AHB_PMA_CM_SR] = REG_FIELD(CMU_R0D0, 24, 31),
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[AHB_SSC_GEN_Z_O_20_13] = REG_FIELD(CMU_R0E8, 8, 15),
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[LANE_PLL_CTRL_RXEQ_RXIDLE] = REG_FIELD(LANE_R048, 8, 15),
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[AHB_PMA_LN_AGC_THSEL_VREGH] = REG_FIELD(LANE_R058, 16, 23),
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[AHB_PMA_LN_GEN3_AGC_SD_THSEL] = REG_FIELD(LANE_R06c, 0, 7),
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[AHB_PMA_LN_RX_SELR_GEN3] = REG_FIELD(LANE_R070, 16, 23),
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[AHB_PMA_LN_TX_DRV] = REG_FIELD(LANE_R19C, 16, 23),
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[P2S_RBUF_PTR_DIFF] = REG_FIELD(COMLANE_R004, 0, 7),
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[CONFIG_VERSION] = REG_FIELD(COMLANE_R138, 16, 23),
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[L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 9, 9),
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[L1_MASTER_CDN] = REG_FIELD(COMLANE_R190, 8, 15),
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[CMU_OK_I_0] = REG_FIELD(COMLANE_R194, 19, 19),
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[COMRXEQ_MS_INIT_CTRL_7_0] = REG_FIELD(COMRXEQ_R004, 24, 31),
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[COMRXEQ_HS_INIT_CAL_7_0] = REG_FIELD(COMRXEQ_R008, 0, 7),
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[COMRXEQ_MS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 8, 15),
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[COMRXEQ_HS_RECAL_CTRL_7_0] = REG_FIELD(COMRXEQ_R00C, 16, 23),
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[COMRXEQ_CSR_ATT_CONFIG] = REG_FIELD(COMRXEQ_R014, 16, 23),
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[COMRXEQ_CSR_EBSTADAPT_WIN_LEN] = REG_FIELD(COMRXEQ_R018, 16, 23),
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[COMRXEQ_CTRL_3_4] = REG_FIELD(COMRXEQ_R01C, 8, 15),
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[COMRXEQ_CTRL_14_15_16] = REG_FIELD(COMRXEQ_R04C, 0, 7),
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[COMRXEQ_CSR_DLEV_ERR_THRESH] = REG_FIELD(COMRXEQ_R088, 16, 23),
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[COMRXEQ_CTRL_25] = REG_FIELD(COMRXEQ_R094, 24, 31),
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[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O] = REG_FIELD(COMRXEQ_R098, 8, 15),
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[COMRXEQ_HS_RCHANGE_CTRL_7_0] = REG_FIELD(COMRXEQ_R098, 16, 23),
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[POR_EN] = REG_FIELD(SERDES_CTRL, 29, 29),
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[TX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 29, 31),
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[RX0_ENABLE] = REG_FIELD(WIZ_LANEXCTL_STS, 13, 15),
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@ -311,9 +418,32 @@ static int serdes_am654_pcie_init(struct serdes_am654 *phy)
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{
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int ret = 0;
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ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
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ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
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ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
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ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
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ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
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ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
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ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
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ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
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ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
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ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
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ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
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ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
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ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
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ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
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ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
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ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
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ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
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ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
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ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
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ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
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ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x1);
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ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
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if (ret)
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return -EIO;
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