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arm64: __clean_dcache_area_pop to take end parameter instead of size

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To be consistent with other functions with similar names and
functionality in cacheflush.h, cache.S, and cachetlb.rst, change
to specify the range in terms of start and end, as opposed to
start and size.

No functional change intended.

Reported-by: Will Deacon <will@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20210524083001.2586635-15-tabba@google.com
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Fuad Tabba 2021-05-24 09:29:57 +01:00 committed by Will Deacon
parent 1f42faf1d2
commit f749448edb
4 changed files with 8 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/include/asm/cacheflush.h
View File

@ -61,7 +61,7 @@ extern void invalidate_icache_range(unsigned long start, unsigned long end);
extern void __flush_dcache_area(unsigned long start, unsigned long end); extern void __flush_dcache_area(unsigned long start, unsigned long end);
extern void __inval_dcache_area(unsigned long start, unsigned long end); extern void __inval_dcache_area(unsigned long start, unsigned long end);
extern void __clean_dcache_area_poc(unsigned long start, unsigned long end); extern void __clean_dcache_area_poc(unsigned long start, unsigned long end);
extern void __clean_dcache_area_pop(void *addr, size_t len); extern void __clean_dcache_area_pop(unsigned long start, unsigned long end);
extern void __clean_dcache_area_pou(void *addr, size_t len); extern void __clean_dcache_area_pou(void *addr, size_t len);
extern long __flush_cache_user_range(unsigned long start, unsigned long end); extern long __flush_cache_user_range(unsigned long start, unsigned long end);
extern void sync_icache_aliases(void *kaddr, unsigned long len); extern void sync_icache_aliases(void *kaddr, unsigned long len);

4
arch/arm64/lib/uaccess_flushcache.c
View File

@ -15,7 +15,7 @@ void memcpy_flushcache(void *dst, const void *src, size_t cnt)
* barrier to order the cache maintenance against the memcpy. * barrier to order the cache maintenance against the memcpy.
*/ */
memcpy(dst, src, cnt); memcpy(dst, src, cnt);
__clean_dcache_area_pop(dst, cnt); __clean_dcache_area_pop((unsigned long)dst, (unsigned long)dst + cnt);
} }
EXPORT_SYMBOL_GPL(memcpy_flushcache); EXPORT_SYMBOL_GPL(memcpy_flushcache);
@ -33,6 +33,6 @@ unsigned long __copy_user_flushcache(void *to, const void __user *from,
rc = raw_copy_from_user(to, from, n); rc = raw_copy_from_user(to, from, n);
/* See above */ /* See above */
__clean_dcache_area_pop(to, n - rc); __clean_dcache_area_pop((unsigned long)to, (unsigned long)to + n - rc);
return rc; return rc;
} }

9
arch/arm64/mm/cache.S
View File

@ -194,16 +194,15 @@ SYM_FUNC_END_PI(__clean_dcache_area_poc)
SYM_FUNC_END(__dma_clean_area) SYM_FUNC_END(__dma_clean_area)
/* /*
* __clean_dcache_area_pop(kaddr, size) * __clean_dcache_area_pop(start, end)
* *
* Ensure that any D-cache lines for the interval [kaddr, kaddr+size) * Ensure that any D-cache lines for the interval [start, end)
* are cleaned to the PoP. * are cleaned to the PoP.
* *
* - kaddr - kernel address * - start - virtual start address of region
* - size - size in question * - end - virtual end address of region
*/ */
SYM_FUNC_START_PI(__clean_dcache_area_pop) SYM_FUNC_START_PI(__clean_dcache_area_pop)
add x1, x0, x1
alternative_if_not ARM64_HAS_DCPOP alternative_if_not ARM64_HAS_DCPOP
b __clean_dcache_area_poc b __clean_dcache_area_poc
alternative_else_nop_endif alternative_else_nop_endif

2
arch/arm64/mm/flush.c
View File

@ -84,7 +84,7 @@ void arch_wb_cache_pmem(void *addr, size_t size)
{ {
/* Ensure order against any prior non-cacheable writes */ /* Ensure order against any prior non-cacheable writes */
dmb(osh); dmb(osh);
__clean_dcache_area_pop(addr, size); __clean_dcache_area_pop((unsigned long)addr, (unsigned long)addr + size);
} }
EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); EXPORT_SYMBOL_GPL(arch_wb_cache_pmem);