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i2c: imx: support slave mode for imx I2C driver
The patch supports slave mode for imx I2C driver Signed-off-by: Biwen Li <biwen.li@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@kernel.org>
This commit is contained in:
Biwen Li
Wolfram Sang
parent
1e04538c75
commit
f7414cd692
@ -675,6 +675,7 @@ config I2C_IMG
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config I2C_IMX
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tristate "IMX I2C interface"
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depends on ARCH_MXC || ARCH_LAYERSCAPE || COLDFIRE
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select I2C_SLAVE
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help
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Say Y here if you want to use the IIC bus controller on
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the Freescale i.MX/MXC, Layerscape or ColdFire processors.
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@ -17,6 +17,7 @@
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* Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*
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*/
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@ -73,6 +74,11 @@
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#define IMX_I2C_I2SR 0x03 /* i2c status */
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#define IMX_I2C_I2DR 0x04 /* i2c transfer data */
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/*
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* All of the layerscape series SoCs support IBIC register.
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*/
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#define IMX_I2C_IBIC 0x05 /* i2c bus interrupt config */
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#define IMX_I2C_REGSHIFT 2
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#define VF610_I2C_REGSHIFT 0
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@ -91,6 +97,7 @@
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#define I2CR_MSTA 0x20
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#define I2CR_IIEN 0x40
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#define I2CR_IEN 0x80
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#define IBIC_BIIE 0x80 /* Bus idle interrupt enable */
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/* register bits different operating codes definition:
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* 1) I2SR: Interrupt flags clear operation differ between SoCs:
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@ -201,6 +208,7 @@ struct imx_i2c_struct {
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struct pinctrl_state *pinctrl_pins_gpio;
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struct imx_i2c_dma *dma;
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struct i2c_client *slave;
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};
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static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
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@ -252,6 +260,11 @@ static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
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return i2c_imx->hwdata->devtype == IMX1_I2C;
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}
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static inline int is_vf610_i2c(struct imx_i2c_struct *i2c_imx)
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{
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return i2c_imx->hwdata->devtype == VF610_I2C;
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}
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static inline void imx_i2c_write_reg(unsigned int val,
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struct imx_i2c_struct *i2c_imx, unsigned int reg)
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{
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@ -264,6 +277,27 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
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return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
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}
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static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
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{
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unsigned int temp;
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/*
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* i2sr_clr_opcode is the value to clear all interrupts. Here we want to
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* clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
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* toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
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*/
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temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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}
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/* Set up i2c controller register and i2c status register to default value. */
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static void i2c_imx_reset_regs(struct imx_i2c_struct *i2c_imx)
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{
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imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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i2c_imx, IMX_I2C_I2CR);
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i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL);
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}
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/* Functions for DMA support */
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static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
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dma_addr_t phy_addr)
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@ -399,19 +433,6 @@ static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
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dma->chan_using = NULL;
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}
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static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits)
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{
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unsigned int temp;
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/*
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* i2sr_clr_opcode is the value to clear all interrupts. Here we want to
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* clear only <bits>, so we write ~i2sr_clr_opcode with just <bits>
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* toggled. This is required because i.MX needs W0C and Vybrid uses W1C.
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*/
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temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
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}
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static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic)
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{
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unsigned long orig_jiffies = jiffies;
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@ -625,18 +646,165 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic)
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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}
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/*
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* Enable bus idle interrupts
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* Note: IBIC register will be cleared after disabled i2c module.
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* All of layerscape series SoCs support IBIC register.
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*/
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static void i2c_imx_enable_bus_idle(struct imx_i2c_struct *i2c_imx)
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{
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if (is_vf610_i2c(i2c_imx)) {
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unsigned int temp;
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_IBIC);
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temp |= IBIC_BIIE;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_IBIC);
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}
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}
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static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx,
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unsigned int status, unsigned int ctl)
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{
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u8 value;
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if (status & I2SR_IAL) { /* Arbitration lost */
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i2c_imx_clear_irq(i2c_imx, I2SR_IAL);
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if (!(status & I2SR_IAAS))
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return IRQ_HANDLED;
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}
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if (status & I2SR_IAAS) { /* Addressed as a slave */
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if (status & I2SR_SRW) { /* Master wants to read from us*/
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dev_dbg(&i2c_imx->adapter.dev, "read requested");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_REQUESTED, &value);
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/* Slave transmit */
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ctl |= I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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/* Send data */
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imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
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} else { /* Master wants to write to us */
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dev_dbg(&i2c_imx->adapter.dev, "write requested");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
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/* Slave receive */
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ctl &= ~I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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/* Dummy read */
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imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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}
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} else if (!(ctl & I2CR_MTX)) { /* Receive mode */
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if (status & I2SR_IBB) { /* No STOP signal detected */
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value = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
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} else { /* STOP signal is detected */
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dev_dbg(&i2c_imx->adapter.dev,
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"STOP signal detected");
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_STOP, &value);
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}
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} else if (!(status & I2SR_RXAK)) { /* Transmit mode received ACK */
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ctl |= I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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i2c_slave_event(i2c_imx->slave, I2C_SLAVE_READ_PROCESSED, &value);
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imx_i2c_write_reg(value, i2c_imx, IMX_I2C_I2DR);
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} else { /* Transmit mode received NAK */
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ctl &= ~I2CR_MTX;
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imx_i2c_write_reg(ctl, i2c_imx, IMX_I2C_I2CR);
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imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
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}
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return IRQ_HANDLED;
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}
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static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx)
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{
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int temp;
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/* Set slave addr. */
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imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx, IMX_I2C_IADR);
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i2c_imx_reset_regs(i2c_imx);
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/* Enable module */
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temp = i2c_imx->hwdata->i2cr_ien_opcode;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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/* Enable interrupt from i2c module */
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temp |= I2CR_IIEN;
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imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
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i2c_imx_enable_bus_idle(i2c_imx);
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}
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static int i2c_imx_reg_slave(struct i2c_client *client)
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{
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struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
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int ret;
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if (i2c_imx->slave)
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return -EBUSY;
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i2c_imx->slave = client;
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/* Resume */
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ret = pm_runtime_get_sync(i2c_imx->adapter.dev.parent);
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if (ret < 0) {
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dev_err(&i2c_imx->adapter.dev, "failed to resume i2c controller");
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return ret;
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}
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i2c_imx_slave_init(i2c_imx);
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return 0;
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}
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static int i2c_imx_unreg_slave(struct i2c_client *client)
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{
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struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(client->adapter);
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int ret;
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if (!i2c_imx->slave)
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return -EINVAL;
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/* Reset slave address. */
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imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
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i2c_imx_reset_regs(i2c_imx);
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i2c_imx->slave = NULL;
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/* Suspend */
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ret = pm_runtime_put_sync(i2c_imx->adapter.dev.parent);
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if (ret < 0)
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dev_err(&i2c_imx->adapter.dev, "failed to suspend i2c controller");
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return ret;
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}
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static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx, unsigned int status)
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{
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/* save status register */
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i2c_imx->i2csr = status;
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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}
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static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
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{
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struct imx_i2c_struct *i2c_imx = dev_id;
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unsigned int temp;
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unsigned int ctl, status;
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temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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if (temp & I2SR_IIF) {
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/* save status register */
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i2c_imx->i2csr = temp;
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status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
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ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
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if (status & I2SR_IIF) {
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i2c_imx_clear_irq(i2c_imx, I2SR_IIF);
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wake_up(&i2c_imx->queue);
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return IRQ_HANDLED;
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if (i2c_imx->slave && !(ctl & I2CR_MSTA))
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return i2c_imx_slave_isr(i2c_imx, status, ctl);
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return i2c_imx_master_isr(i2c_imx, status);
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}
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return IRQ_NONE;
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@ -1014,6 +1182,10 @@ fail0:
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dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
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(result < 0) ? "error" : "success msg",
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(result < 0) ? result : num);
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/* After data is transferred, switch to slave mode(as a receiver) */
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if (i2c_imx->slave)
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i2c_imx_slave_init(i2c_imx);
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return (result < 0) ? result : num;
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}
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@ -1127,6 +1299,8 @@ static const struct i2c_algorithm i2c_imx_algo = {
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.master_xfer = i2c_imx_xfer,
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.master_xfer_atomic = i2c_imx_xfer_atomic,
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.functionality = i2c_imx_func,
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.reg_slave = i2c_imx_reg_slave,
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.unreg_slave = i2c_imx_unreg_slave,
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};
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static int i2c_imx_probe(struct platform_device *pdev)
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@ -1216,10 +1390,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
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clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb);
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i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk));
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/* Set up chip registers to defaults */
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imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN,
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i2c_imx, IMX_I2C_I2CR);
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imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR);
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i2c_imx_reset_regs(i2c_imx);
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/* Init optional bus recovery function */
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ret = i2c_imx_init_recovery_info(i2c_imx, pdev);
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