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drm/amd/display: reset dcn31 SMU mailbox on failures
commit 83293f7f3d
upstream.
Otherwise future commands may fail as well leading to downstream
problems that look like they stemmed from a timeout the first time
but really didn't.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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parent
8a17a077e7
commit
f71c91ed1d
@ -119,6 +119,12 @@ int dcn31_smu_send_msg_with_param(
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result = dcn31_smu_wait_for_response(clk_mgr, 10, 200000);
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if (result == VBIOSSMC_Result_Failed) {
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ASSERT(0);
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REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Result_OK);
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return -1;
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}
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if (IS_SMU_TIMEOUT(result)) {
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ASSERT(0);
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dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
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