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iommu/vt-d: Factor out invalidation descriptor composition
Separate the logic for constructing IOTLB and device TLB invalidation descriptors from the qi_flush interfaces. New helpers, qi_desc(), are introduced to encapsulate this common functionality. Moving descriptor composition code to new helpers enables its reuse in the upcoming qi_batch interfaces. No functional changes are intended. Signed-off-by: Tina Zhang <tina.zhang@intel.com> Link: https://lore.kernel.org/r/20240815065221.50328-2-tina.zhang@intel.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Tina Zhang
Joerg Roedel
parent
1f5e307ca1
commit
f701c9f36b
@ -1526,24 +1526,9 @@ void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid, u8 fm,
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void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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unsigned int size_order, u64 type)
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{
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u8 dw = 0, dr = 0;
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struct qi_desc desc;
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int ih = 0;
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if (cap_write_drain(iommu->cap))
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dw = 1;
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if (cap_read_drain(iommu->cap))
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dr = 1;
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desc.qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
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| QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
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desc.qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
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| QI_IOTLB_AM(size_order);
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_desc_iotlb(iommu, did, addr, size_order, type, &desc);
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qi_submit_sync(iommu, &desc, 1, 0);
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}
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@ -1561,20 +1546,7 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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if (!(iommu->gcmd & DMA_GCMD_TE))
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return;
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if (mask) {
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addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
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desc.qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
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} else
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desc.qw1 = QI_DEV_IOTLB_ADDR(addr);
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if (qdep >= QI_DEV_IOTLB_MAX_INVS)
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qdep = 0;
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desc.qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
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QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
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desc.qw2 = 0;
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desc.qw3 = 0;
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qi_desc_dev_iotlb(sid, pfsid, qdep, addr, mask, &desc);
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qi_submit_sync(iommu, &desc, 1, 0);
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}
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@ -1594,28 +1566,7 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
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return;
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}
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if (npages == -1) {
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desc.qw0 = QI_EIOTLB_PASID(pasid) |
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QI_EIOTLB_DID(did) |
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
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QI_EIOTLB_TYPE;
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desc.qw1 = 0;
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} else {
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int mask = ilog2(__roundup_pow_of_two(npages));
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unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
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if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
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addr = ALIGN_DOWN(addr, align);
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desc.qw0 = QI_EIOTLB_PASID(pasid) |
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QI_EIOTLB_DID(did) |
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QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
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QI_EIOTLB_TYPE;
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desc.qw1 = QI_EIOTLB_ADDR(addr) |
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QI_EIOTLB_IH(ih) |
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QI_EIOTLB_AM(mask);
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}
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qi_desc_piotlb(did, pasid, addr, npages, ih, &desc);
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qi_submit_sync(iommu, &desc, 1, 0);
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}
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@ -1623,7 +1574,6 @@ void qi_flush_piotlb(struct intel_iommu *iommu, u16 did, u32 pasid, u64 addr,
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void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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u32 pasid, u16 qdep, u64 addr, unsigned int size_order)
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{
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unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
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struct qi_desc desc = {.qw1 = 0, .qw2 = 0, .qw3 = 0};
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/*
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@ -1635,40 +1585,9 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *iommu, u16 sid, u16 pfsid,
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if (!(iommu->gcmd & DMA_GCMD_TE))
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return;
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desc.qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
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QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
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QI_DEV_IOTLB_PFSID(pfsid);
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/*
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* If S bit is 0, we only flush a single page. If S bit is set,
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* The least significant zero bit indicates the invalidation address
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* range. VT-d spec 6.5.2.6.
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* e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
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* size order = 0 is PAGE_SIZE 4KB
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* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
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* ECAP.
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*/
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if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
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pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
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addr, size_order);
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/* Take page address */
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desc.qw1 = QI_DEV_EIOTLB_ADDR(addr);
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if (size_order) {
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/*
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* Existing 0s in address below size_order may be the least
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* significant bit, we must set them to 1s to avoid having
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* smaller size than desired.
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*/
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desc.qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
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VTD_PAGE_SHIFT);
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/* Clear size_order bit to indicate size */
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desc.qw1 &= ~mask;
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/* Set the S bit to indicate flushing more than 1 page */
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desc.qw1 |= QI_DEV_EIOTLB_SIZE;
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}
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qi_desc_dev_iotlb_pasid(sid, pfsid, pasid,
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qdep, addr, size_order,
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&desc);
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qi_submit_sync(iommu, &desc, 1, 0);
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}
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@ -1066,6 +1066,115 @@ static inline unsigned long nrpages_to_size(unsigned long npages)
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return npages << VTD_PAGE_SHIFT;
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}
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static inline void qi_desc_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
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unsigned int size_order, u64 type,
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struct qi_desc *desc)
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{
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u8 dw = 0, dr = 0;
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int ih = 0;
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if (cap_write_drain(iommu->cap))
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dw = 1;
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if (cap_read_drain(iommu->cap))
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dr = 1;
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desc->qw0 = QI_IOTLB_DID(did) | QI_IOTLB_DR(dr) | QI_IOTLB_DW(dw)
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| QI_IOTLB_GRAN(type) | QI_IOTLB_TYPE;
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desc->qw1 = QI_IOTLB_ADDR(addr) | QI_IOTLB_IH(ih)
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| QI_IOTLB_AM(size_order);
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desc->qw2 = 0;
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desc->qw3 = 0;
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}
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static inline void qi_desc_dev_iotlb(u16 sid, u16 pfsid, u16 qdep, u64 addr,
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unsigned int mask, struct qi_desc *desc)
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{
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if (mask) {
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addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1;
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desc->qw1 = QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE;
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} else {
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desc->qw1 = QI_DEV_IOTLB_ADDR(addr);
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}
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if (qdep >= QI_DEV_IOTLB_MAX_INVS)
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qdep = 0;
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desc->qw0 = QI_DEV_IOTLB_SID(sid) | QI_DEV_IOTLB_QDEP(qdep) |
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QI_DIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid);
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desc->qw2 = 0;
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desc->qw3 = 0;
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}
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static inline void qi_desc_piotlb(u16 did, u32 pasid, u64 addr,
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unsigned long npages, bool ih,
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struct qi_desc *desc)
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{
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if (npages == -1) {
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desc->qw0 = QI_EIOTLB_PASID(pasid) |
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QI_EIOTLB_DID(did) |
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QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
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QI_EIOTLB_TYPE;
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desc->qw1 = 0;
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} else {
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int mask = ilog2(__roundup_pow_of_two(npages));
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unsigned long align = (1ULL << (VTD_PAGE_SHIFT + mask));
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if (WARN_ON_ONCE(!IS_ALIGNED(addr, align)))
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addr = ALIGN_DOWN(addr, align);
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desc->qw0 = QI_EIOTLB_PASID(pasid) |
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QI_EIOTLB_DID(did) |
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QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
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QI_EIOTLB_TYPE;
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desc->qw1 = QI_EIOTLB_ADDR(addr) |
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QI_EIOTLB_IH(ih) |
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QI_EIOTLB_AM(mask);
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}
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}
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static inline void qi_desc_dev_iotlb_pasid(u16 sid, u16 pfsid, u32 pasid,
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u16 qdep, u64 addr,
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unsigned int size_order,
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struct qi_desc *desc)
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{
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unsigned long mask = 1UL << (VTD_PAGE_SHIFT + size_order - 1);
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desc->qw0 = QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) |
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QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE |
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QI_DEV_IOTLB_PFSID(pfsid);
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/*
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* If S bit is 0, we only flush a single page. If S bit is set,
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* The least significant zero bit indicates the invalidation address
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* range. VT-d spec 6.5.2.6.
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* e.g. address bit 12[0] indicates 8KB, 13[0] indicates 16KB.
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* size order = 0 is PAGE_SIZE 4KB
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* Max Invs Pending (MIP) is set to 0 for now until we have DIT in
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* ECAP.
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*/
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if (!IS_ALIGNED(addr, VTD_PAGE_SIZE << size_order))
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pr_warn_ratelimited("Invalidate non-aligned address %llx, order %d\n",
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addr, size_order);
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/* Take page address */
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desc->qw1 = QI_DEV_EIOTLB_ADDR(addr);
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if (size_order) {
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/*
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* Existing 0s in address below size_order may be the least
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* significant bit, we must set them to 1s to avoid having
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* smaller size than desired.
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*/
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desc->qw1 |= GENMASK_ULL(size_order + VTD_PAGE_SHIFT - 1,
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VTD_PAGE_SHIFT);
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/* Clear size_order bit to indicate size */
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desc->qw1 &= ~mask;
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/* Set the S bit to indicate flushing more than 1 page */
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desc->qw1 |= QI_DEV_EIOTLB_SIZE;
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}
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}
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/* Convert value to context PASID directory size field coding. */
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#define context_pdts(pds) (((pds) & 0x7) << 9)
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