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ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk

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Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
This commit is contained in:
Eugeniy Paltsev 2017-08-14 19:12:11 +03:00 committed by Vineet Gupta
parent 9926c29f74
commit f6a09bace0
2 changed files with 18 additions and 4 deletions
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11
arch/arc/boot/dts/axc003.dtsi
View File

@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk {
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <90000000>;
clock-frequency = <33333333>;
};
core_clk: core-clk@80 {
compatible = "snps,axs10x-arc-pll-clock";
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {

11
arch/arc/boot/dts/axc003_idu.dtsi
View File

@ -24,10 +24,17 @@
ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
core_clk: core_clk {
input_clk: input-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
clock-frequency = <33333333>;
};
core_clk: core-clk@80 {
compatible = "snps,axs10x-arc-pll-clock";
reg = <0x80 0x10>, <0x100 0x10>;
#clock-cells = <0>;
clocks = <&input_clk>;
};
core_intc: archs-intc@cpu {