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net: phy: bcm7xxx: Add EPHY entry for 72165
72165 is a 16nm process SoC with a 10/100 integrated Ethernet PHY, create a new macro and set of functions for this different process type. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210917181551.2836036-1-f.fainelli@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Florian Fainelli
Jakub Kicinski
parent
1a575cde59
commit
f68d08c437
@ -398,6 +398,190 @@ static int bcm7xxx_28nm_ephy_config_init(struct phy_device *phydev)
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return bcm7xxx_28nm_ephy_apd_enable(phydev);
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}
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static int bcm7xxx_16nm_ephy_afe_config(struct phy_device *phydev)
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{
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int tmp, rcalcode, rcalnewcodelp, rcalnewcode11, rcalnewcode11d2;
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/* Reset PHY */
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tmp = genphy_soft_reset(phydev);
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if (tmp)
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return tmp;
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/* Reset AFE and PLL */
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bcm_phy_write_exp_sel(phydev, 0x0003, 0x0006);
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/* Clear reset */
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bcm_phy_write_exp_sel(phydev, 0x0003, 0x0000);
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/* Write PLL/AFE control register to select 54MHz crystal */
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bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0000);
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bcm_phy_write_misc(phydev, 0x0031, 0x0000, 0x044a);
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/* Change Ka,Kp,Ki to pdiv=1 */
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bcm_phy_write_misc(phydev, 0x0033, 0x0002, 0x71a1);
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/* Configuration override */
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bcm_phy_write_misc(phydev, 0x0033, 0x0001, 0x8000);
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/* Change PLL_NDIV and PLL_NUDGE */
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bcm_phy_write_misc(phydev, 0x0031, 0x0001, 0x2f68);
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bcm_phy_write_misc(phydev, 0x0031, 0x0002, 0x0000);
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/* Reference frequency is 54Mhz, config_mode[15:14] = 3 (low
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* phase)
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*/
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bcm_phy_write_misc(phydev, 0x0030, 0x0003, 0xc036);
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/* Initialize bypass mode */
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bcm_phy_write_misc(phydev, 0x0032, 0x0003, 0x0000);
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/* Bypass code, default: VCOCLK enabled */
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bcm_phy_write_misc(phydev, 0x0033, 0x0000, 0x0002);
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/* LDOs at default setting */
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bcm_phy_write_misc(phydev, 0x0030, 0x0002, 0x01c0);
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/* Release PLL reset */
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bcm_phy_write_misc(phydev, 0x0030, 0x0001, 0x0001);
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/* Bandgap curvature correction to correct default */
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bcm_phy_write_misc(phydev, 0x0038, 0x0000, 0x0010);
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/* Run RCAL */
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x0038);
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003b);
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udelay(2);
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, 0x003f);
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mdelay(5);
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/* AFE_CAL_CONFIG_0, Vref=1000, Target=10, averaging enabled */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x1c82);
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/* AFE_CAL_CONFIG_0, no reset and analog powerup */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e82);
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udelay(2);
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/* AFE_CAL_CONFIG_0, start calibration */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f82);
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udelay(100);
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/* AFE_CAL_CONFIG_0, clear start calibration, set HiBW */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9e86);
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udelay(2);
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/* AFE_CAL_CONFIG_0, start calibration with hi BW mode set */
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bcm_phy_write_misc(phydev, 0x0039, 0x0001, 0x9f86);
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udelay(100);
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/* Adjust 10BT amplitude additional +7% and 100BT +2% */
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bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7ea);
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/* Adjust 1G mode amplitude and 1G testmode1 */
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bcm_phy_write_misc(phydev, 0x0038, 0x0002, 0xede0);
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/* Read CORE_EXPA9 */
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tmp = bcm_phy_read_exp(phydev, 0x00a9);
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/* CORE_EXPA9[6:1] is rcalcode[5:0] */
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rcalcode = (tmp & 0x7e) / 2;
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/* Correct RCAL code + 1 is -1% rprogr, LP: +16 */
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rcalnewcodelp = rcalcode + 16;
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/* Correct RCAL code + 1 is -15 rprogr, 11: +10 */
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rcalnewcode11 = rcalcode + 10;
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/* Saturate if necessary */
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if (rcalnewcodelp > 0x3f)
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rcalnewcodelp = 0x3f;
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if (rcalnewcode11 > 0x3f)
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rcalnewcode11 = 0x3f;
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/* REXT=1 BYP=1 RCAL_st1<5:0>=new rcal code */
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tmp = 0x00f8 + rcalnewcodelp * 256;
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/* Program into AFE_CAL_CONFIG_2 */
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bcm_phy_write_misc(phydev, 0x0039, 0x0003, tmp);
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/* AFE_BIAS_CONFIG_0 10BT bias code (Bias: E4) */
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bcm_phy_write_misc(phydev, 0x0038, 0x0001, 0xe7e4);
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/* invert adc clock output and 'adc refp ldo current To correct
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* default
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*/
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bcm_phy_write_misc(phydev, 0x003b, 0x0000, 0x8002);
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/* 100BT stair case, high BW, 1G stair case, alternate encode */
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bcm_phy_write_misc(phydev, 0x003c, 0x0003, 0xf882);
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/* 1000BT DAC transition method per Erol, bits[32], DAC Shuffle
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* sequence 1 + 10BT imp adjust bits
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*/
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bcm_phy_write_misc(phydev, 0x003d, 0x0000, 0x3201);
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/* Non-overlap fix */
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bcm_phy_write_misc(phydev, 0x003a, 0x0002, 0x0c00);
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/* pwdb override (rxconfig<5>) to turn on RX LDO indpendent of
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* pwdb controls from DSP_TAP10
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*/
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bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0020);
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/* Remove references to channel 2 and 3 */
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bcm_phy_write_misc(phydev, 0x003b, 0x0002, 0x0000);
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bcm_phy_write_misc(phydev, 0x003b, 0x0003, 0x0000);
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/* Set cal_bypassb bit rxconfig<43> */
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bcm_phy_write_misc(phydev, 0x003a, 0x0003, 0x0800);
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udelay(2);
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/* Revert pwdb_override (rxconfig<5>) to 0 so that the RX pwr
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* is controlled by DSP.
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*/
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bcm_phy_write_misc(phydev, 0x003a, 0x0001, 0x0000);
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/* Drop LSB */
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rcalnewcode11d2 = (rcalnewcode11 & 0xfffe) / 2;
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tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0001);
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/* Clear bits [11:5] */
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tmp &= ~0xfe0;
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/* set txcfg_ch0<5>=1 (enable + set local rcal) */
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tmp |= 0x0020 | (rcalnewcode11d2 * 64);
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bcm_phy_write_misc(phydev, 0x003d, 0x0001, tmp);
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bcm_phy_write_misc(phydev, 0x003d, 0x0002, tmp);
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tmp = bcm_phy_read_misc(phydev, 0x003d, 0x0000);
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/* set txcfg<45:44>=11 (enable Rextra + invert fullscaledetect)
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*/
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tmp &= ~0x3000;
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tmp |= 0x3000;
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bcm_phy_write_misc(phydev, 0x003d, 0x0000, tmp);
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return 0;
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}
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static int bcm7xxx_16nm_ephy_config_init(struct phy_device *phydev)
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{
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int ret, val;
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ret = bcm7xxx_16nm_ephy_afe_config(phydev);
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if (ret)
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return ret;
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ret = bcm_phy_set_eee(phydev, true);
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if (ret)
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return ret;
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ret = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
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if (ret < 0)
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return ret;
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val = ret;
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/* Auto power down of DLL enabled,
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* TXC/RXC disabled during auto power down.
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*/
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val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
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val |= BIT(8);
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ret = bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
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if (ret < 0)
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return ret;
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return bcm_phy_enable_apd(phydev, true);
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}
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static int bcm7xxx_16nm_ephy_resume(struct phy_device *phydev)
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{
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int ret;
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/* Re-apply workarounds coming out suspend/resume */
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ret = bcm7xxx_16nm_ephy_config_init(phydev);
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if (ret)
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return ret;
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return genphy_config_aneg(phydev);
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}
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static int bcm7xxx_28nm_ephy_resume(struct phy_device *phydev)
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{
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int ret;
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@ -610,9 +794,25 @@ static void bcm7xxx_28nm_remove(struct phy_device *phydev)
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.resume = bcm7xxx_config_init, \
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}
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#define BCM7XXX_16NM_EPHY(_oui, _name) \
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{ \
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.phy_id = (_oui), \
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.phy_id_mask = 0xfffffff0, \
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.name = _name, \
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/* PHY_BASIC_FEATURES */ \
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.flags = PHY_IS_INTERNAL, \
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.probe = bcm7xxx_28nm_probe, \
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.remove = bcm7xxx_28nm_remove, \
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.config_init = bcm7xxx_16nm_ephy_config_init, \
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.config_aneg = genphy_config_aneg, \
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.read_status = genphy_read_status, \
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.resume = bcm7xxx_16nm_ephy_resume, \
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}
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static struct phy_driver bcm7xxx_driver[] = {
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BCM7XXX_28NM_EPHY(PHY_ID_BCM72113, "Broadcom BCM72113"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM72116, "Broadcom BCM72116"),
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BCM7XXX_16NM_EPHY(PHY_ID_BCM72165, "Broadcom BCM72165"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM7255, "Broadcom BCM7255"),
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BCM7XXX_28NM_EPHY(PHY_ID_BCM7260, "Broadcom BCM7260"),
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@ -635,6 +835,7 @@ static struct phy_driver bcm7xxx_driver[] = {
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static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
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{ PHY_ID_BCM72113, 0xfffffff0 },
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{ PHY_ID_BCM72116, 0xfffffff0, },
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{ PHY_ID_BCM72165, 0xfffffff0, },
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{ PHY_ID_BCM7250, 0xfffffff0, },
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{ PHY_ID_BCM7255, 0xfffffff0, },
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{ PHY_ID_BCM7260, 0xfffffff0, },
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@ -32,6 +32,7 @@
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#define PHY_ID_BCM72113 0x35905310
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#define PHY_ID_BCM72116 0x35905350
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#define PHY_ID_BCM72165 0x35905340
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#define PHY_ID_BCM7250 0xae025280
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#define PHY_ID_BCM7255 0xae025120
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#define PHY_ID_BCM7260 0xae025190
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