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phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845
QMP V3 UNI PHY is a single lane USB3 PHY without support for DisplayPort (DP). Main difference from DP combo QMPv3 PHY is that UNI PHY doesn't have dual RX/TX lanes and no separate DP_COM block for configuration related to type-c or DP. Also remove "qcom,qmp-v3-usb3-phy" compatible string which was earlier added for sdm845 only as there wouldn't be any user of same. While at it, fix has_pwrdn_delay attribute for USB-DP PHY configuration and. Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Manu Gautam <mgautam@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Manu Gautam
Kishon Vijay Abraham I
parent
7f08020741
commit
f6721e5c0b
@ -490,6 +490,118 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
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QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
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};
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static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
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/* FLL settings */
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
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/* Lock Det settings */
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
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};
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/* struct qmp_phy_cfg - per-PHY initialization config */
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struct qmp_phy_cfg {
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/* phy-type - PCIE/UFS/USB */
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@ -766,6 +878,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
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.pwrdn_ctrl = SW_PWRDN,
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.mask_pcs_ready = PHYSTATUS,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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@ -774,6 +887,35 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
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.rx_b_lane_offset = 0x400,
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};
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static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
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.tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
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.rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
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.pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
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.clk_list = qmp_v3_phy_clk_l,
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.num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = msm8996_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(msm8996_phy_vreg_l),
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.regs = qmp_v3_usb3phy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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.mask_pcs_ready = PHYSTATUS,
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.has_pwrdn_delay = true,
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.pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
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.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
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};
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static void qcom_qmp_phy_configure(void __iomem *base,
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const unsigned int *regs,
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const struct qmp_phy_init_tbl tbl[],
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@ -1375,8 +1517,11 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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.compatible = "qcom,ipq8074-qmp-pcie-phy",
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.data = &ipq8074_pciephy_cfg,
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}, {
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.compatible = "qcom,qmp-v3-usb3-phy",
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.compatible = "qcom,sdm845-qmp-usb3-phy",
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.data = &qmp_v3_usb3phy_cfg,
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}, {
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.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
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.data = &qmp_v3_usb3_uniphy_cfg,
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},
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{ },
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};
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@ -214,6 +214,8 @@
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#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
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#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
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#define QSERDES_V3_RX_RX_TERM_BW 0x07c
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#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
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#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0
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#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8
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#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc
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#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4
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@ -227,6 +229,7 @@
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#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c
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#define QSERDES_V3_RX_RX_BAND 0x110
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#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c
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#define QSERDES_V3_RX_RX_MODE_00 0x164
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/* Only for QMP V3 PHY - PCS registers */
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#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
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@ -273,6 +276,8 @@
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#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
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#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
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#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
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#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
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/* Only for QMP V3 PHY - PCS_MISC registers */
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#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
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