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irqchip: bcm7120-l2: Eliminate bad IRQ check

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This check may be prone to race conditions, e.g.

1) Some external event (e.g. GPIO level) causes an IRQ to become pending
2) Peripheral asserts the L2 IRQ
3) CPU takes an interrupt
4) The event from #1 goes away
5) bcm7120_l2_intc_irq_handle() reads back a 0 status

Unlike the hardware supported by brcmstb-l2, the bcm7120-l2 controller
does not latch the IRQ status.  Bits can change if the inputs to the
controller change.  Also, do_bad_IRQ() is an ARM-specific macro.

So let's just nuke it.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/1415342669-30640-7-git-send-email-cernekee@gmail.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Kevin Cernekee 2014-11-06 22:44:21 -08:00 committed by Jason Cooper
parent 05f1275745
commit f668f074ff
1 changed files with 2 additions and 11 deletions
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13
drivers/irqchip/irq-bcm7120-l2.c
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@ -27,8 +27,6 @@
#include "irqchip.h"
#include <asm/mach/irq.h>
/* Register offset in the L2 interrupt controller */
#define IRQEN 0x00
#define IRQSTAT 0x04
@ -51,19 +49,12 @@ static void bcm7120_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
chained_irq_enter(chip, desc);
status = __raw_readl(b->base + IRQSTAT);
if (status == 0) {
do_bad_IRQ(irq, desc);
goto out;
}
do {
while (status) {
irq = ffs(status) - 1;
status &= ~(1 << irq);
generic_handle_irq(irq_find_mapping(b->domain, irq));
} while (status);
}
out:
chained_irq_exit(chip, desc);
}