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ALSA: hda - Move low level functions to hda_controller
Share more code from hda_intel. This moves the link control and initialization to hda_controller. The code will also be used by an hda platform driver. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Dylan Reid
Takashi Iwai
parent
f19c3ec21b
commit
f43923ff2c
@ -1039,7 +1039,7 @@ static int azx_alloc_cmd_io(struct azx *chip)
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}
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EXPORT_SYMBOL_GPL(azx_alloc_cmd_io);
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void azx_init_cmd_io(struct azx *chip)
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static void azx_init_cmd_io(struct azx *chip)
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{
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int timeout;
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@ -1102,7 +1102,7 @@ void azx_init_cmd_io(struct azx *chip)
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}
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EXPORT_SYMBOL_GPL(azx_init_cmd_io);
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void azx_free_cmd_io(struct azx *chip)
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static void azx_free_cmd_io(struct azx *chip)
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{
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spin_lock_irq(&chip->reg_lock);
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/* disable ringbuffer DMAs */
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@ -1574,5 +1574,178 @@ void azx_free_stream_pages(struct azx *chip)
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}
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EXPORT_SYMBOL_GPL(azx_free_stream_pages);
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/*
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* Lowlevel interface
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*/
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/* enter link reset */
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void azx_enter_link_reset(struct azx *chip)
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{
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unsigned long timeout;
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/* reset controller */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
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time_before(jiffies, timeout))
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usleep_range(500, 1000);
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}
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EXPORT_SYMBOL_GPL(azx_enter_link_reset);
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/* exit link reset */
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static void azx_exit_link_reset(struct azx *chip)
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{
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unsigned long timeout;
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azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while (!azx_readb(chip, GCTL) &&
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time_before(jiffies, timeout))
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usleep_range(500, 1000);
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}
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/* reset codec link */
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static int azx_reset(struct azx *chip, int full_reset)
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{
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if (!full_reset)
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goto __skip;
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/* clear STATESTS */
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azx_writew(chip, STATESTS, STATESTS_INT_MASK);
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/* reset controller */
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azx_enter_link_reset(chip);
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/* delay for >= 100us for codec PLL to settle per spec
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* Rev 0.9 section 5.5.1
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*/
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usleep_range(500, 1000);
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/* Bring controller out of reset */
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azx_exit_link_reset(chip);
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/* Brent Chartrand said to wait >= 540us for codecs to initialize */
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usleep_range(1000, 1200);
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__skip:
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/* check to see if controller is ready */
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if (!azx_readb(chip, GCTL)) {
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dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
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return -EBUSY;
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}
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/* Accept unsolicited responses */
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if (!chip->single_cmd)
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
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ICH6_GCTL_UNSOL);
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/* detect codecs */
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if (!chip->codec_mask) {
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chip->codec_mask = azx_readw(chip, STATESTS);
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dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
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chip->codec_mask);
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}
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return 0;
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}
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/* enable interrupts */
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static void azx_int_enable(struct azx *chip)
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{
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/* enable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
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ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
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}
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/* disable interrupts */
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static void azx_int_disable(struct azx *chip)
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{
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int i;
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/* disable interrupts in stream descriptor */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) &
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~SD_INT_MASK);
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}
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/* disable SIE for all streams */
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azx_writeb(chip, INTCTL, 0);
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/* disable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
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~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
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}
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/* clear interrupts */
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static void azx_int_clear(struct azx *chip)
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{
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int i;
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/* clear stream status */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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}
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/* clear STATESTS */
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azx_writew(chip, STATESTS, STATESTS_INT_MASK);
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/* clear rirb status */
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azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
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/* clear int status */
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azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
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}
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/*
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* reset and start the controller registers
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*/
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void azx_init_chip(struct azx *chip, int full_reset)
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{
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if (chip->initialized)
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return;
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/* reset controller */
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azx_reset(chip, full_reset);
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/* initialize interrupts */
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azx_int_clear(chip);
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azx_int_enable(chip);
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/* initialize the codec command I/O */
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if (!chip->single_cmd)
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azx_init_cmd_io(chip);
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/* program the position buffer */
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azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
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azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
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chip->initialized = 1;
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}
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EXPORT_SYMBOL_GPL(azx_init_chip);
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void azx_stop_chip(struct azx *chip)
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{
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if (!chip->initialized)
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return;
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/* disable interrupts */
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azx_int_disable(chip);
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azx_int_clear(chip);
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/* disable CORB/RIRB */
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azx_free_cmd_io(chip);
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/* disable position buffer */
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azx_writel(chip, DPLBASE, 0);
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azx_writel(chip, DPUBASE, 0);
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chip->initialized = 0;
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}
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Common HDA driver funcitons");
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@ -50,11 +50,14 @@ void azx_free_stream_pages(struct azx *chip);
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/*
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* CORB / RIRB interface
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*/
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void azx_init_cmd_io(struct azx *chip);
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void azx_free_cmd_io(struct azx *chip);
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void azx_update_rirb(struct azx *chip);
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int azx_send_cmd(struct hda_bus *bus, unsigned int val);
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unsigned int azx_get_response(struct hda_bus *bus,
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unsigned int addr);
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/* Low level azx interface */
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void azx_init_chip(struct azx *chip, int full_reset);
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void azx_stop_chip(struct azx *chip);
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void azx_enter_link_reset(struct azx *chip);
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#endif /* __SOUND_HDA_CONTROLLER_H */
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@ -340,159 +340,6 @@ static int azx_acquire_irq(struct azx *chip, int do_disconnect);
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static void azx_power_notify(struct hda_bus *bus, bool power_up);
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#endif
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/* enter link reset */
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static void azx_enter_link_reset(struct azx *chip)
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{
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unsigned long timeout;
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/* reset controller */
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
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time_before(jiffies, timeout))
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usleep_range(500, 1000);
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}
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/* exit link reset */
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static void azx_exit_link_reset(struct azx *chip)
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{
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unsigned long timeout;
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azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
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timeout = jiffies + msecs_to_jiffies(100);
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while (!azx_readb(chip, GCTL) &&
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time_before(jiffies, timeout))
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usleep_range(500, 1000);
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}
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/* reset codec link */
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static int azx_reset(struct azx *chip, int full_reset)
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{
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if (!full_reset)
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goto __skip;
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/* clear STATESTS */
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azx_writew(chip, STATESTS, STATESTS_INT_MASK);
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/* reset controller */
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azx_enter_link_reset(chip);
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/* delay for >= 100us for codec PLL to settle per spec
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* Rev 0.9 section 5.5.1
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*/
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usleep_range(500, 1000);
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/* Bring controller out of reset */
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azx_exit_link_reset(chip);
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/* Brent Chartrand said to wait >= 540us for codecs to initialize */
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usleep_range(1000, 1200);
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__skip:
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/* check to see if controller is ready */
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if (!azx_readb(chip, GCTL)) {
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dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
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return -EBUSY;
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}
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/* Accept unsolicited responses */
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if (!chip->single_cmd)
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azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
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ICH6_GCTL_UNSOL);
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/* detect codecs */
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if (!chip->codec_mask) {
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chip->codec_mask = azx_readw(chip, STATESTS);
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dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
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chip->codec_mask);
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}
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return 0;
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}
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/*
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* Lowlevel interface
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*/
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/* enable interrupts */
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static void azx_int_enable(struct azx *chip)
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{
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/* enable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
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ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
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}
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/* disable interrupts */
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static void azx_int_disable(struct azx *chip)
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{
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int i;
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/* disable interrupts in stream descriptor */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(chip, azx_dev, SD_CTL,
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azx_sd_readb(chip, azx_dev, SD_CTL) &
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~SD_INT_MASK);
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}
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/* disable SIE for all streams */
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azx_writeb(chip, INTCTL, 0);
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/* disable controller CIE and GIE */
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azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
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~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
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}
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/* clear interrupts */
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static void azx_int_clear(struct azx *chip)
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{
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int i;
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/* clear stream status */
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for (i = 0; i < chip->num_streams; i++) {
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struct azx_dev *azx_dev = &chip->azx_dev[i];
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azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
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}
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/* clear STATESTS */
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azx_writew(chip, STATESTS, STATESTS_INT_MASK);
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/* clear rirb status */
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azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
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/* clear int status */
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azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
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}
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/*
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* reset and start the controller registers
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*/
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static void azx_init_chip(struct azx *chip, int full_reset)
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{
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if (chip->initialized)
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return;
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/* reset controller */
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azx_reset(chip, full_reset);
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/* initialize interrupts */
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azx_int_clear(chip);
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azx_int_enable(chip);
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/* initialize the codec command I/O */
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if (!chip->single_cmd)
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azx_init_cmd_io(chip);
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/* program the position buffer */
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azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
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azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
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chip->initialized = 1;
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}
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/*
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* initialize the PCI registers
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*/
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@ -660,8 +507,6 @@ static int probe_codec(struct azx *chip, int addr)
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return 0;
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}
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static void azx_stop_chip(struct azx *chip);
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static void azx_bus_reset(struct hda_bus *bus)
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{
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struct azx *chip = bus->private_data;
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@ -942,26 +787,6 @@ static int azx_acquire_irq(struct azx *chip, int do_disconnect)
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return 0;
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}
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static void azx_stop_chip(struct azx *chip)
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{
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if (!chip->initialized)
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return;
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/* disable interrupts */
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azx_int_disable(chip);
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azx_int_clear(chip);
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/* disable CORB/RIRB */
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azx_free_cmd_io(chip);
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/* disable position buffer */
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azx_writel(chip, DPLBASE, 0);
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azx_writel(chip, DPUBASE, 0);
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chip->initialized = 0;
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}
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#ifdef CONFIG_PM
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/* power-up/down the controller */
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static void azx_power_notify(struct hda_bus *bus, bool power_up)
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