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V4L/DVB (9514): cx18: Fix PLL freq computation for debug display

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cx18: Fix PLL freq computation for debug display.
The code to compute the PLL freq from register values was storing an
intermediate 56 bit result in a 32 bit type, causing a nonsense value to
be displayed.

Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Andy Walls 2008-11-02 18:54:10 -03:00 committed by Mauro Carvalho Chehab
parent 69acdf1e5a
commit f4167342b5
1 changed files with 2 additions and 3 deletions
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5
drivers/media/video/cx18/cx18-av-core.c
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@ -273,10 +273,9 @@ void cx18_av_std_setup(struct cx18 *cx)
pll_int, pll_frac, pll_post);
if (pll_post) {
int fin, fsc;
int pll = 28636363L * ((((u64)pll_int) << 25) + pll_frac);
int fin, fsc, pll;
pll >>= 25;
pll = (28636364L * ((((u64)pll_int) << 25) + pll_frac)) >> 25;
pll /= pll_post;
CX18_DEBUG_INFO("PLL = %d.%06d MHz\n",
pll / 1000000, pll % 1000000);