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x86/intel_rdt: Support L3 cache performance event of Broadwell
Broadwell microarchitecture supports pseudo-locking. Add support for the L3 cache related performance events of these systems so that the success of pseudo-locking can be measured more accurately on these platforms. Signed-off-by: Reinette Chatre <reinette.chatre@intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: fenghua.yu@intel.com Cc: tony.luck@intel.com Cc: vikas.shivappa@linux.intel.com Cc: gavin.hindman@intel.com Cc: jithu.joseph@intel.com Cc: dave.hansen@intel.com Cc: hpa@zytor.com Link: https://lkml.kernel.org/r/36c1414e9bd17c3faf440f32b644b9c879bcbae2.1529706536.git.reinette.chatre@intel.com
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@ -850,6 +850,8 @@ static int measure_cycles_lat_fn(void *_plr)
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static int measure_cycles_perf_fn(void *_plr)
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{
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unsigned long long l3_hits = 0, l3_miss = 0;
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u64 l3_hit_bits = 0, l3_miss_bits = 0;
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struct pseudo_lock_region *plr = _plr;
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unsigned long long l2_hits, l2_miss;
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u64 l2_hit_bits, l2_miss_bits;
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@ -883,6 +885,16 @@ static int measure_cycles_perf_fn(void *_plr)
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* L2_HIT 02H
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* L1_MISS 08H
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* L2_MISS 10H
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*
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* On Broadwell Microarchitecture the MEM_LOAD_UOPS_RETIRED event
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* has two "no fix" errata associated with it: BDM35 and BDM100. On
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* this platform we use the following events instead:
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* L2_RQSTS 24H (Documented in https://download.01.org/perfmon/BDW/)
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* REFERENCES FFH
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* MISS 3FH
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* LONGEST_LAT_CACHE 2EH (Documented in SDM)
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* REFERENCE 4FH
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* MISS 41H
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*/
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/*
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@ -901,6 +913,14 @@ static int measure_cycles_perf_fn(void *_plr)
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l2_hit_bits = (0x52ULL << 16) | (0x2 << 8) | 0xd1;
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l2_miss_bits = (0x52ULL << 16) | (0x10 << 8) | 0xd1;
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break;
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case INTEL_FAM6_BROADWELL_X:
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/* On BDW the l2_hit_bits count references, not hits */
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l2_hit_bits = (0x52ULL << 16) | (0xff << 8) | 0x24;
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l2_miss_bits = (0x52ULL << 16) | (0x3f << 8) | 0x24;
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/* On BDW the l3_hit_bits count references, not hits */
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l3_hit_bits = (0x52ULL << 16) | (0x4f << 8) | 0x2e;
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l3_miss_bits = (0x52ULL << 16) | (0x41 << 8) | 0x2e;
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break;
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default:
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goto out;
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}
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@ -917,9 +937,21 @@ static int measure_cycles_perf_fn(void *_plr)
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0 + 1, 0x0);
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if (l3_hit_bits > 0) {
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 2, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 3, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0 + 2, 0x0);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_PERFCTR0 + 3, 0x0);
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}
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/* Set and enable the L2 counters */
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0, l2_hit_bits);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1, l2_miss_bits);
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if (l3_hit_bits > 0) {
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 2,
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l3_hit_bits);
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 3,
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l3_miss_bits);
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}
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mem_r = plr->kmem;
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size = plr->size;
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line_size = plr->line_size;
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@ -937,11 +969,35 @@ static int measure_cycles_perf_fn(void *_plr)
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l2_hit_bits & ~(0x40ULL << 16));
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 1,
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l2_miss_bits & ~(0x40ULL << 16));
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if (l3_hit_bits > 0) {
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 2,
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l3_hit_bits & ~(0x40ULL << 16));
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pseudo_wrmsrl_notrace(MSR_ARCH_PERFMON_EVENTSEL0 + 3,
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l3_miss_bits & ~(0x40ULL << 16));
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}
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l2_hits = native_read_pmc(0);
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l2_miss = native_read_pmc(1);
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if (l3_hit_bits > 0) {
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l3_hits = native_read_pmc(2);
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l3_miss = native_read_pmc(3);
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}
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wrmsr(MSR_MISC_FEATURE_CONTROL, 0x0, 0x0);
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local_irq_enable();
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/*
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* On BDW we count references and misses, need to adjust. Sometimes
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* the "hits" counter is a bit more than the references, for
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* example, x references but x + 1 hits. To not report invalid
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* hit values in this case we treat that as misses eaqual to
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* references.
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*/
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if (boot_cpu_data.x86_model == INTEL_FAM6_BROADWELL_X)
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l2_hits -= (l2_miss > l2_hits ? l2_hits : l2_miss);
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trace_pseudo_lock_l2(l2_hits, l2_miss);
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if (l3_hit_bits > 0) {
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if (boot_cpu_data.x86_model == INTEL_FAM6_BROADWELL_X)
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l3_hits -= (l3_miss > l3_hits ? l3_hits : l3_miss);
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trace_pseudo_lock_l3(l3_hits, l3_miss);
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}
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out:
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plr->thread_done = 1;
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@ -25,6 +25,16 @@ TRACE_EVENT(pseudo_lock_l2,
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TP_printk("hits=%llu miss=%llu",
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__entry->l2_hits, __entry->l2_miss));
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TRACE_EVENT(pseudo_lock_l3,
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TP_PROTO(u64 l3_hits, u64 l3_miss),
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TP_ARGS(l3_hits, l3_miss),
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TP_STRUCT__entry(__field(u64, l3_hits)
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__field(u64, l3_miss)),
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TP_fast_assign(__entry->l3_hits = l3_hits;
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__entry->l3_miss = l3_miss;),
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TP_printk("hits=%llu miss=%llu",
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__entry->l3_hits, __entry->l3_miss));
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#endif /* _TRACE_PSEUDO_LOCK_H */
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#undef TRACE_INCLUDE_PATH
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