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Merge branch 'v6.11/bindings' into v6.11/drivers
* v6.11/bindings: dt-bindings: clock: meson: a1: peripherals: support sys_pll input dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
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commit
f34da56094
@ -30,6 +30,8 @@ properties:
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- description: input fixed pll div7
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- description: input hifi pll
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- description: input oscillator (usually at 24MHz)
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- description: input sys pll
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minItems: 6 # sys_pll is optional
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clock-names:
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items:
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@ -39,6 +41,8 @@ properties:
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- const: fclk_div7
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- const: hifi_pll
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- const: xtal
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- const: sys_pll
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minItems: 6 # sys_pll is optional
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required:
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- compatible
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@ -65,9 +69,10 @@ examples:
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<&clkc_pll CLKID_FCLK_DIV5>,
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<&clkc_pll CLKID_FCLK_DIV7>,
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<&clkc_pll CLKID_HIFI_PLL>,
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<&xtal>;
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<&xtal>,
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<&clkc_pll CLKID_SYS_PLL>;
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clock-names = "fclk_div2", "fclk_div3",
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"fclk_div5", "fclk_div7",
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"hifi_pll", "xtal";
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"hifi_pll", "xtal", "sys_pll";
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};
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};
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@ -26,11 +26,15 @@ properties:
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items:
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- description: input fixpll_in
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- description: input hifipll_in
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- description: input syspll_in
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minItems: 2 # syspll_in is optional
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clock-names:
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items:
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- const: fixpll_in
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- const: hifipll_in
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- const: syspll_in
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minItems: 2 # syspll_in is optional
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required:
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- compatible
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@ -53,7 +57,8 @@ examples:
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reg = <0 0x7c80 0 0x18c>;
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#clock-cells = <1>;
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clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
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<&clkc_periphs CLKID_HIFIPLL_IN>;
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clock-names = "fixpll_in", "hifipll_in";
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<&clkc_periphs CLKID_HIFIPLL_IN>,
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<&clkc_periphs CLKID_SYSPLL_IN>;
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clock-names = "fixpll_in", "hifipll_in", "syspll_in";
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};
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};
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@ -164,5 +164,6 @@
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#define CLKID_DMC_SEL 151
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#define CLKID_DMC_DIV 152
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#define CLKID_DMC_SEL2 153
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#define CLKID_SYS_PLL_DIV16 154
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#endif /* __A1_PERIPHERALS_CLKC_H */
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@ -21,5 +21,6 @@
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#define CLKID_FCLK_DIV5 8
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#define CLKID_FCLK_DIV7 9
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#define CLKID_HIFI_PLL 10
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#define CLKID_SYS_PLL 11
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#endif /* __A1_PLL_CLKC_H */
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