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MIPS: Detect MIPSr6 Virtual Processor support
MIPSr6 introduces support for "Virtual Processors", which are conceptually similar to VPEs from the now-deprecated MT ASE. Detect whether the system supports VPs using the VP bit in Config5, adding cpu_has_vp for use by later patches. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Steven J. Hill <sjhill@realitydiluted.com> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12327/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -311,6 +311,10 @@
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#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
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#endif
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#ifndef cpu_has_vp
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#define cpu_has_vp (cpu_data[0].options & MIPS_CPU_VP)
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#endif
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#ifndef cpu_has_userlocal
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#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
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#endif
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@ -390,6 +390,7 @@ enum cpu_type_enum {
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#define MIPS_CPU_FTLB 0x20000000000ull /* CPU has Fixed-page-size TLB */
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#define MIPS_CPU_NAN_LEGACY 0x40000000000ull /* Legacy NaN implemented */
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#define MIPS_CPU_NAN_2008 0x80000000000ull /* 2008 NaN implemented */
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#define MIPS_CPU_VP 0x100000000000ull /* MIPSr6 Virtual Processors (multi-threading) */
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/*
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* CPU ASE encodings
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@ -623,6 +623,7 @@
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#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
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#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
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#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
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#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
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#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
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#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
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#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
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@ -796,6 +796,8 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
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if (config5 & MIPS_CONF5_MVH)
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c->options |= MIPS_CPU_XPA;
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#endif
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if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
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c->options |= MIPS_CPU_VP;
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return config5 & MIPS_CONF_M;
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}
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