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Merge branch 'lpc32xx/fixes' of git://git.antcom.de/linux-2.6 into fixes

Browse Source 
* 'lpc32xx/fixes' of git://git.antcom.de/linux-2.6: (5 commits)
  ARM: LPC32xx: serial.c: Fixed loop limit
  ARM: LPC32xx: serial.c: HW bug workaround
  ARM: LPC32xx: irq.c: Clear latched event
  ARM: LPC32xx: Fix interrupt controller init
  ARM: LPC32xx: Fix irq on GPI_28

Update to Linux 3.3-rc5

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-02-27 17:44:06 +00:00
commit f2273ecd9a
202 changed files with 1593 additions and 1108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
MAINTAINERS
View File

@ -269,7 +269,6 @@ S: Orphan
F: drivers/platform/x86/wmi.c
AD1889 ALSA SOUND DRIVER
M: Kyle McMartin <kyle@mcmartin.ca>
M: Thibaut Varene <T-Bone@parisc-linux.org>
W: http://wiki.parisc-linux.org/AD1889
L: linux-parisc@vger.kernel.org
@ -3047,7 +3046,6 @@ F: drivers/hwspinlock/hwspinlock_*
F: include/linux/hwspinlock.h
HARMONY SOUND DRIVER
M: Kyle McMartin <kyle@mcmartin.ca>
L: linux-parisc@vger.kernel.org
S: Maintained
F: sound/parisc/harmony.*
@ -5000,9 +4998,8 @@ F: Documentation/blockdev/paride.txt
F: drivers/block/paride/
PARISC ARCHITECTURE
M: Kyle McMartin <kyle@mcmartin.ca>
M: Helge Deller <deller@gmx.de>
M: "James E.J. Bottomley" <jejb@parisc-linux.org>
M: Helge Deller <deller@gmx.de>
L: linux-parisc@vger.kernel.org
W: http://www.parisc-linux.org/
Q: http://patchwork.kernel.org/project/linux-parisc/list/
@ -5861,7 +5858,7 @@ S: Maintained
F: drivers/mmc/host/sdhci-spear.c
SECURITY SUBSYSTEM
M: James Morris <jmorris@namei.org>
M: James Morris <james.l.morris@oracle.com>
L: linux-security-module@vger.kernel.org (suggested Cc:)
T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git
W: http://security.wiki.kernel.org/
@ -5874,7 +5871,7 @@ S: Supported
SELINUX SECURITY MODULE
M: Stephen Smalley <sds@tycho.nsa.gov>
M: James Morris <jmorris@namei.org>
M: James Morris <james.l.morris@oracle.com>
M: Eric Paris <eparis@parisplace.org>
L: selinux@tycho.nsa.gov (subscribers-only, general discussion)
W: http://selinuxproject.org

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 3
PATCHLEVEL = 3
SUBLEVEL = 0
EXTRAVERSION = -rc4
EXTRAVERSION = -rc5
NAME = Saber-toothed Squirrel
# *DOCUMENTATION*

7
arch/arm/common/it8152.c
View File

@ -320,13 +320,6 @@ err0:
return -EBUSY;
}
/*
* If we set up a device for bus mastering, we need to check the latency
* timer as we don't have even crappy BIOSes to set it properly.
* The implementation is from arch/i386/pci/i386.c
*/
unsigned int pcibios_max_latency = 255;
/* ITE bridge requires setting latency timer to avoid early bus access
termination by PCI bus master devices
*/

3
arch/arm/common/pl330.c
View File

@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
struct pl330_thread *thrd = ch_id;
struct pl330_dmac *pl330;
unsigned long flags;
int ret = 0, active = thrd->req_running;
int ret = 0, active;
if (!thrd || thrd->free || thrd->dmac->state == DYING)
return -EINVAL;
pl330 = thrd->dmac;
active = thrd->req_running;
spin_lock_irqsave(&pl330->lock, flags);

5
arch/arm/include/asm/assembler.h
View File

@ -137,6 +137,11 @@
disable_irq
.endm
.macro save_and_disable_irqs_notrace, oldcpsr
mrs \oldcpsr, cpsr
disable_irq_notrace
.endm
/*
* Restore interrupt state previously stored in a register. We don't
* guarantee that this will preserve the flags.

2
arch/arm/include/asm/hardware/pl330.h
View File

@ -41,7 +41,7 @@ enum pl330_dstcachectrl {
DCCTRL1, /* Bufferable only */
DCCTRL2, /* Cacheable, but do not allocate */
DCCTRL3, /* Cacheable and bufferable, but do not allocate */
DINVALID1 = 8,
DINVALID1, /* AWCACHE = 0x1000 */
DINVALID2,
DCCTRL6, /* Cacheable write-through, allocate on writes only */
DCCTRL7, /* Cacheable write-back, allocate on writes only */

1
arch/arm/include/asm/processor.h
View File

@ -22,6 +22,7 @@
#include <asm/hw_breakpoint.h>
#include <asm/ptrace.h>
#include <asm/types.h>
#include <asm/system.h>
#ifdef __KERNEL__
#define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \

9
arch/arm/kernel/ptrace.c
View File

@ -23,6 +23,7 @@
#include <linux/perf_event.h>
#include <linux/hw_breakpoint.h>
#include <linux/regset.h>
#include <linux/audit.h>
#include <asm/pgtable.h>
#include <asm/system.h>
@ -904,6 +905,12 @@ long arch_ptrace(struct task_struct *child, long request,
return ret;
}
#ifdef __ARMEB__
#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
#else
#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
#endif
asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
{
unsigned long ip;
@ -918,7 +925,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
if (!ip)
audit_syscall_exit(regs);
else
audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0,
audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
if (!test_thread_flag(TIF_SYSCALL_TRACE))

2
arch/arm/kernel/smp_twd.c
View File

@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = {
static int twd_cpufreq_init(void)
{
if (!IS_ERR(twd_clk))
if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
return cpufreq_register_notifier(&twd_cpufreq_nb,
CPUFREQ_TRANSITION_NOTIFIER);

2
arch/arm/mach-lpc32xx/include/mach/irqs.h
View File

@ -61,7 +61,7 @@
*/
#define IRQ_LPC32XX_JTAG_COMM_TX LPC32XX_SIC1_IRQ(1)
#define IRQ_LPC32XX_JTAG_COMM_RX LPC32XX_SIC1_IRQ(2)
#define IRQ_LPC32XX_GPI_11 LPC32XX_SIC1_IRQ(4)
#define IRQ_LPC32XX_GPI_28 LPC32XX_SIC1_IRQ(4)
#define IRQ_LPC32XX_TS_P LPC32XX_SIC1_IRQ(6)
#define IRQ_LPC32XX_TS_IRQ LPC32XX_SIC1_IRQ(7)
#define IRQ_LPC32XX_TS_AUX LPC32XX_SIC1_IRQ(8)

25
arch/arm/mach-lpc32xx/irq.c
View File

@ -118,6 +118,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
.event_group = &lpc32xx_event_pin_regs,
.mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
},
[IRQ_LPC32XX_GPI_28] = {
.event_group = &lpc32xx_event_pin_regs,
.mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
},
[IRQ_LPC32XX_GPIO_00] = {
.event_group = &lpc32xx_event_int_regs,
.mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
@ -305,9 +309,18 @@ static int lpc32xx_irq_wake(struct irq_data *d, unsigned int state)
if (state)
eventreg |= lpc32xx_events[d->irq].mask;
else
else {
eventreg &= ~lpc32xx_events[d->irq].mask;
/*
* When disabling the wakeup, clear the latched
* event
*/
__raw_writel(lpc32xx_events[d->irq].mask,
lpc32xx_events[d->irq].
event_group->rawstat_reg);
}
__raw_writel(eventreg,
lpc32xx_events[d->irq].event_group->enab_reg);
@ -380,13 +393,15 @@ void __init lpc32xx_init_irq(void)
/* Setup SIC1 */
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
__raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
__raw_writel(SIC1_ATR_DEFAULT,
LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
/* Setup SIC2 */
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
__raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
__raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
__raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
__raw_writel(SIC2_ATR_DEFAULT,
LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
/* Configure supported IRQ's */
for (i = 0; i < NR_IRQS; i++) {

20
arch/arm/mach-lpc32xx/serial.c
View File

@ -88,6 +88,7 @@ struct uartinit {
char *uart_ck_name;
u32 ck_mode_mask;
void __iomem *pdiv_clk_reg;
resource_size_t mapbase;
};
static struct uartinit uartinit_data[] __initdata = {
@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
.ck_mode_mask =
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
.mapbase = LPC32XX_UART5_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
.ck_mode_mask =
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
.mapbase = LPC32XX_UART3_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
.ck_mode_mask =
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
.mapbase = LPC32XX_UART4_BASE,
},
#endif
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
.ck_mode_mask =
LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
.mapbase = LPC32XX_UART6_BASE,
},
#endif
};
@ -165,11 +170,24 @@ void __init lpc32xx_serial_init(void)
/* pre-UART clock divider set to 1 */
__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
/*
* Force a flush of the RX FIFOs to work around a
* HW bug
*/
puart = uartinit_data[i].mapbase;
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
j = LPC32XX_SUART_FIFO_SIZE;
while (j--)
tmp = __raw_readl(
LPC32XX_UART_DLL_FIFO(puart));
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
}
/* This needs to be done after all UART clocks are setup */
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
/* Force a flush of the RX FIFOs to work around a HW bug */
puart = serial_std_platform_data[i].mapbase;
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));

2
arch/arm/mach-omap2/voltagedomains3xxx_data.c
View File

@ -108,6 +108,7 @@ void __init omap3xxx_voltagedomains_init(void)
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
#ifdef CONFIG_PM_OPP
if (cpu_is_omap3630()) {
omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
@ -115,6 +116,7 @@ void __init omap3xxx_voltagedomains_init(void)
omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
}
#endif
if (cpu_is_omap3517() || cpu_is_omap3505())
voltdms = voltagedomains_am35xx;

2
arch/arm/mach-omap2/voltagedomains44xx_data.c
View File

@ -100,9 +100,11 @@ void __init omap44xx_voltagedomains_init(void)
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
#ifdef CONFIG_PM_OPP
omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data;
omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data;
omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data;
#endif
for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;

29
arch/arm/mach-shmobile/board-ag5evm.c
View File

@ -30,6 +30,7 @@
#include <linux/serial_sci.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/mmc/host.h>
@ -37,7 +38,6 @@
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/sh_clk.h>
#include <linux/dma-mapping.h>
#include <video/sh_mobile_lcdc.h>
#include <video/sh_mipi_dsi.h>
#include <sound/sh_fsi.h>
@ -159,19 +159,12 @@ static struct resource sh_mmcif_resources[] = {
},
};
static struct sh_mmcif_dma sh_mmcif_dma = {
.chan_priv_rx = {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
},
.chan_priv_tx = {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
},
};
static struct sh_mmcif_plat_data sh_mmcif_platdata = {
.sup_pclk = 0,
.ocr = MMC_VDD_165_195,
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
.dma = &sh_mmcif_dma,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
static struct platform_device mmc_device = {
@ -321,12 +314,11 @@ static struct resource mipidsi0_resources[] = {
},
};
#define DSI0PHYCR 0xe615006c
static int sh_mipi_set_dot_clock(struct platform_device *pdev,
void __iomem *base,
int enable)
{
struct clk *pck;
struct clk *pck, *phy;
int ret;
pck = clk_get(&pdev->dev, "dsip_clk");
@ -335,18 +327,27 @@ static int sh_mipi_set_dot_clock(struct platform_device *pdev,
goto sh_mipi_set_dot_clock_pck_err;
}
phy = clk_get(&pdev->dev, "dsiphy_clk");
if (IS_ERR(phy)) {
ret = PTR_ERR(phy);
goto sh_mipi_set_dot_clock_phy_err;
}
if (enable) {
clk_set_rate(pck, clk_round_rate(pck, 24000000));
__raw_writel(0x2a809010, DSI0PHYCR);
clk_set_rate(phy, clk_round_rate(pck, 510000000));
clk_enable(pck);
clk_enable(phy);
} else {
clk_disable(pck);
clk_disable(phy);
}
ret = 0;
clk_put(phy);
sh_mipi_set_dot_clock_phy_err:
clk_put(pck);
sh_mipi_set_dot_clock_pck_err:
return ret;
}

12
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -295,15 +295,6 @@ static struct resource sh_mmcif_resources[] = {
},
};
static struct sh_mmcif_dma sh_mmcif_dma = {
.chan_priv_rx = {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
},
.chan_priv_tx = {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
},
};
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
.ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@ -311,7 +302,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
MMC_CAP_8_BIT_DATA |
MMC_CAP_NEEDS_POLL,
.get_cd = slot_cn7_get_cd,
.dma = &sh_mmcif_dma,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
static struct platform_device sh_mmcif_device = {

3
arch/arm/mach-shmobile/board-kota2.c
View File

@ -143,11 +143,10 @@ static struct gpio_keys_button gpio_buttons[] = {
static struct gpio_keys_platform_data gpio_key_info = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
.poll_interval = 250, /* polled for now */
};
static struct platform_device gpio_keys_device = {
.name = "gpio-keys-polled", /* polled for now */
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &gpio_key_info,

95
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -43,7 +43,6 @@
#include <linux/smsc911x.h>
#include <linux/sh_intc.h>
#include <linux/tca6416_keypad.h>
#include <linux/usb/r8a66597.h>
#include <linux/usb/renesas_usbhs.h>
#include <linux/dma-mapping.h>
@ -145,11 +144,6 @@
* 1-2 short | VBUS 5V | Host
* open | external VBUS | Function
*
* *1
* CN31 is used as
* CONFIG_USB_R8A66597_HCD Host
* CONFIG_USB_RENESAS_USBHS Function
*
* CAUTION
*
* renesas_usbhs driver can use external interrupt mode
@ -161,15 +155,6 @@
* mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
* because Touchscreen is using IRQ7-PORT40.
* It is impossible to use IRQ7 demux on this board.
*
* We can use external interrupt mode USB-Function on "USB1".
* USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
* But don't select both drivers in same time.
* These uses same IRQ number for request_irq(), and aren't supporting
* IRQF_SHARED / IORESOURCE_IRQ_SHAREABLE.
*
* Actually these are old/new version of USB driver.
* This mean its register will be broken if it supports shared IRQ,
*/
/*
@ -207,6 +192,16 @@
*
*/
/*
* FSI - AK4642
*
* it needs amixer settings for playing
*
* amixer set "Headphone" on
* amixer set "HPOUTL Mixer DACH" on
* amixer set "HPOUTR Mixer DACH" on
*/
/*
* FIXME !!
*
@ -676,51 +671,16 @@ static struct platform_device usbhs0_device = {
* Use J30 to select between Host and Function. This setting
* can however not be detected by software. Hotplug of USBHS1
* is provided via IRQ8.
*
* Current USB1 works as "USB Host".
* - set J30 "short"
*
* If you want to use it as "USB gadget",
* - J30 "open"
* - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
* - add .get_vbus = usbhs_get_vbus in usbhs1_private
*/
#define IRQ8 evt2irq(0x0300)
/* USBHS1 USB Host support via r8a66597_hcd */
static void usb1_host_port_power(int port, int power)
{
if (!power) /* only power-on is supported for now */
return;
/* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
__raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
}
static struct r8a66597_platdata usb1_host_data = {
.on_chip = 1,
.port_power = usb1_host_port_power,
};
static struct resource usb1_host_resources[] = {
[0] = {
.name = "USBHS1",
.start = 0xe68b0000,
.end = 0xe68b00e6 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device usb1_host_device = {
.name = "r8a66597_hcd",
.id = 1,
.dev = {
.dma_mask = NULL, /* not use dma */
.coherent_dma_mask = 0xffffffff,
.platform_data = &usb1_host_data,
},
.num_resources = ARRAY_SIZE(usb1_host_resources),
.resource = usb1_host_resources,
};
/* USBHS1 USB Function support via renesas_usbhs */
#define USB_PHY_MODE (1 << 4)
#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
#define USB_PHY_ON (1 << 1)
@ -776,7 +736,7 @@ static void usbhs1_hardware_exit(struct platform_device *pdev)
static int usbhs1_get_id(struct platform_device *pdev)
{
return USBHS_GADGET;
return USBHS_HOST;
}
static u32 usbhs1_pipe_cfg[] = {
@ -807,7 +767,6 @@ static struct usbhs_private usbhs1_private = {
.hardware_exit = usbhs1_hardware_exit,
.get_id = usbhs1_get_id,
.phy_reset = usbhs_phy_reset,
.get_vbus = usbhs_get_vbus,
},
.driver_param = {
.buswait_bwait = 4,
@ -1184,15 +1143,6 @@ static struct resource sh_mmcif_resources[] = {
},
};
static struct sh_mmcif_dma sh_mmcif_dma = {
.chan_priv_rx = {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
},
.chan_priv_tx = {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
},
};
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
.ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@ -1200,7 +1150,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
MMC_CAP_8_BIT_DATA |
MMC_CAP_NEEDS_POLL,
.get_cd = slot_cn7_get_cd,
.dma = &sh_mmcif_dma,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
static struct platform_device sh_mmcif_device = {
@ -1311,7 +1262,6 @@ static struct platform_device *mackerel_devices[] __initdata = {
&nor_flash_device,
&smc911x_device,
&lcdc_device,
&usb1_host_device,
&usbhs1_device,
&usbhs0_device,
&leds_device,
@ -1473,9 +1423,6 @@ static void __init mackerel_init(void)
gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */
gpio_request(GPIO_FN_IDIN_1_113, NULL);
/* USB phy tweak to make the r8a66597_hcd host driver work */
__raw_writew(0x8a0a, 0xe6058130); /* USBCR4 */
/* enable FSI2 port A (ak4643) */
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);

113
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -365,6 +365,114 @@ static struct clk div6_clks[DIV6_NR] = {
dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
};
/* DSI DIV */
static unsigned long dsiphy_recalc(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base);
/* FIXME */
if (!(value & 0x000B8000))
return clk->parent->rate;
value &= 0x3f;
value += 1;
if ((value < 12) ||
(value > 33)) {
pr_err("DSIPHY has wrong value (%d)", value);
return 0;
}
return clk->parent->rate / value;
}
static long dsiphy_round_rate(struct clk *clk, unsigned long rate)
{
return clk_rate_mult_range_round(clk, 12, 33, rate);
}
static void dsiphy_disable(struct clk *clk)
{
u32 value;
value = __raw_readl(clk->mapping->base);
value &= ~0x000B8000;
__raw_writel(value , clk->mapping->base);
}
static int dsiphy_enable(struct clk *clk)
{
u32 value;
int multi;
value = __raw_readl(clk->mapping->base);
multi = (value & 0x3f) + 1;
if ((multi < 12) || (multi > 33))
return -EIO;
__raw_writel(value | 0x000B8000, clk->mapping->base);
return 0;
}
static int dsiphy_set_rate(struct clk *clk, unsigned long rate)
{
u32 value;
int idx;
idx = rate / clk->parent->rate;
if ((idx < 12) || (idx > 33))
return -EINVAL;
idx += -1;
value = __raw_readl(clk->mapping->base);
value = (value & ~0x3f) + idx;
__raw_writel(value, clk->mapping->base);
return 0;
}
static struct clk_ops dsiphy_clk_ops = {
.recalc = dsiphy_recalc,
.round_rate = dsiphy_round_rate,
.set_rate = dsiphy_set_rate,
.enable = dsiphy_enable,
.disable = dsiphy_disable,
};
static struct clk_mapping dsi0phy_clk_mapping = {
.phys = DSI0PHYCR,
.len = 4,
};
static struct clk_mapping dsi1phy_clk_mapping = {
.phys = DSI1PHYCR,
.len = 4,
};
static struct clk dsi0phy_clk = {
.ops = &dsiphy_clk_ops,
.parent = &div6_clks[DIV6_DSI0P], /* late install */
.mapping = &dsi0phy_clk_mapping,
};
static struct clk dsi1phy_clk = {
.ops = &dsiphy_clk_ops,
.parent = &div6_clks[DIV6_DSI1P], /* late install */
.mapping = &dsi1phy_clk_mapping,
};
static struct clk *late_main_clks[] = {
&dsi0phy_clk,
&dsi1phy_clk,
};
enum { MSTP001,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
MSTP219,
@ -429,6 +537,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@ -504,6 +614,9 @@ void __init sh73a0_clock_init(void)
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
ret = clk_register(late_main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)

6
arch/arm/mach-shmobile/include/mach/sh73a0.h
View File

@ -515,8 +515,8 @@ enum {
SHDMA_SLAVE_MMCIF_RX,
};
/* PINT interrupts are located at Linux IRQ 768 and up */
#define SH73A0_PINT0_IRQ(irq) ((irq) + 768)
#define SH73A0_PINT1_IRQ(irq) ((irq) + 800)
/* PINT interrupts are located at Linux IRQ 800 and up */
#define SH73A0_PINT0_IRQ(irq) ((irq) + 800)
#define SH73A0_PINT1_IRQ(irq) ((irq) + 832)
#endif /* __ASM_SH73A0_H__ */

2
arch/arm/mach-shmobile/intc-sh73a0.c
View File

@ -19,6 +19,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/sh_intc.h>
@ -445,6 +446,7 @@ void __init sh73a0_init_irq(void)
setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
WARN_ON(irq_alloc_desc_at(n, numa_node_id()) != n);
irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
handle_level_irq, "level");
set_irq_flags(n, IRQF_VALID); /* yuck */

2
arch/arm/mach-shmobile/pfc-r8a7779.c
View File

@ -2120,7 +2120,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_AUDATA3, 0, 0, 0 }
},
{ PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3, 1, 1, 1, 1, 1, 1, 3, 3, 1,
3, 1, 1, 1, 1, 1, 1, 3, 3,
1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
/* IP4_31_29 [3] */
FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,

41
arch/arm/mach-shmobile/pfc-sh7372.c
View File

@ -23,6 +23,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <mach/irqs.h>
#include <mach/sh7372.h>
#define CPU_ALL_PORT(fn, pfx, sfx) \
@ -1594,6 +1595,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
};
static struct pinmux_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
.reserved_id = PINMUX_RESERVED,
@ -1614,6 +1652,9 @@ static struct pinmux_info sh7372_pinmux_info = {
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
.gpio_irq = pinmux_irqs,
.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
};
void sh7372_pinmux_init(void)

2
arch/arm/mach-shmobile/smp-sh73a0.c
View File

@ -80,7 +80,7 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
if (((__raw_readw(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
if (((__raw_readl(__io(PSTR)) >> (4 * cpu)) & 3) == 3)
__raw_writel(1 << cpu, __io(WUPCR)); /* wake up */
else
__raw_writel(1 << cpu, __io(SRESCR)); /* reset */

3
arch/arm/mm/Kconfig
View File

@ -631,7 +631,8 @@ comment "Processor Features"
config ARM_LPAE
bool "Support for the Large Physical Address Extension"
depends on MMU && CPU_V7
depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
!CPU_32v4 && !CPU_32v3
help
Say Y if you have an ARMv7 processor supporting the LPAE page
table format and you would like to access memory beyond the

2
arch/arm/mm/cache-v7.S
View File

@ -55,7 +55,7 @@ loop1:
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
#ifdef CONFIG_PREEMPT
save_and_disable_irqs r9 @ make cssr&csidr read atomic
save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr

2
arch/c6x/boot/Makefile
View File

@ -13,7 +13,7 @@ obj-y += linked_dtb.o
endif
$(obj)/%.dtb: $(src)/dts/%.dts FORCE
$(call cmd,dtc)
$(call if_changed_dep,dtc)
quiet_cmd_cp = CP $< $@$2
cmd_cp = cat $< >$@$2 || (rm -f $@ && echo false)

3
arch/m68k/include/asm/mcf_pgtable.h
View File

@ -78,7 +78,8 @@
| CF_PAGE_READABLE \
| CF_PAGE_WRITABLE \
| CF_PAGE_EXEC \
| CF_PAGE_SYSTEM)
| CF_PAGE_SYSTEM \
| CF_PAGE_SHARED)
#define PAGE_COPY __pgprot(CF_PAGE_VALID \
| CF_PAGE_ACCESSED \

9
arch/m68k/mm/mcfmmu.c
View File

@ -87,7 +87,7 @@ void __init paging_init(void)
int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
{
unsigned long flags, mmuar;
unsigned long flags, mmuar, mmutr;
struct mm_struct *mm;
pgd_t *pgd;
pmd_t *pmd;
@ -137,9 +137,10 @@ int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
if (!pte_dirty(*pte) && !KMAPAREA(mmuar))
set_pte(pte, pte_wrprotect(*pte));
mmu_write(MMUTR, (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) |
(((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK)
>> CF_PAGE_MMUTR_SHIFT) | MMUTR_V);
mmutr = (mmuar & PAGE_MASK) | (asid << MMUTR_IDN) | MMUTR_V;
if ((mmuar < TASK_UNMAPPED_BASE) || (mmuar >= TASK_SIZE))
mmutr |= (pte->pte & CF_PAGE_MMUTR_MASK) >> CF_PAGE_MMUTR_SHIFT;
mmu_write(MMUTR, mmutr);
mmu_write(MMUDR, (pte_val(*pte) & PAGE_MASK) |
((pte->pte) & CF_PAGE_MMUDR_MASK) | MMUDR_SZ_8KB | MMUDR_X);

4
arch/m68k/platform/coldfire/entry.S
View File

@ -136,7 +136,7 @@ Luser_return:
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
movel %d1,%a0
movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
moveb %a0@(TINFO_FLAGS+3),%d1 /* thread_info->flags (low 8 bits) */
jne Lwork_to_do /* still work to do */
Lreturn:
@ -148,8 +148,6 @@ Lwork_to_do:
btst #TIF_NEED_RESCHED,%d1
jne reschedule
/* GERG: do we need something here for TRACEing?? */
Lsignal_return:
subql #4,%sp /* dummy return address */
SAVE_SWITCH_STACK

2
arch/powerpc/kernel/entry_32.S
View File

@ -1213,7 +1213,7 @@ do_user_signal: /* r10 contains MSR_KERNEL here */
stw r3,_TRAP(r1)
2: addi r3,r1,STACK_FRAME_OVERHEAD
mr r4,r9
bl do_signal
bl do_notify_resume
REST_NVGPRS(r1)
b recheck

6
arch/powerpc/kernel/entry_64.S
View File

@ -751,12 +751,16 @@ user_work:
andi. r0,r4,_TIF_NEED_RESCHED
beq 1f
li r5,1
TRACE_AND_RESTORE_IRQ(r5);
bl .schedule
b .ret_from_except_lite
1: bl .save_nvgprs
li r5,1
TRACE_AND_RESTORE_IRQ(r5);
addi r3,r1,STACK_FRAME_OVERHEAD
bl .do_signal
bl .do_notify_resume
b .ret_from_except
unrecov_restore:

2
arch/powerpc/kernel/exceptions-64s.S
View File

@ -774,8 +774,8 @@ alignment_common:
program_check_common:
EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
bl .save_nvgprs
addi r3,r1,STACK_FRAME_OVERHEAD
DISABLE_INTS
addi r3,r1,STACK_FRAME_OVERHEAD
bl .program_check_exception
b .ret_from_except

12
arch/powerpc/kernel/signal.c
View File

@ -11,6 +11,7 @@
#include <linux/tracehook.h>
#include <linux/signal.h>
#include <linux/key.h>
#include <asm/hw_breakpoint.h>
#include <asm/uaccess.h>
#include <asm/unistd.h>
@ -113,8 +114,9 @@ static void check_syscall_restart(struct pt_regs *regs, struct k_sigaction *ka,
}
}
static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
static int do_signal(struct pt_regs *regs)
{
sigset_t *oldset;
siginfo_t info;
int signr;
struct k_sigaction ka;
@ -123,7 +125,7 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
if (current_thread_info()->local_flags & _TLF_RESTORE_SIGMASK)
oldset = &current->saved_sigmask;
else if (!oldset)
else
oldset = &current->blocked;
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
@ -191,14 +193,16 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
return ret;
}
void do_signal(struct pt_regs *regs, unsigned long thread_info_flags)
void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags)
{
if (thread_info_flags & _TIF_SIGPENDING)
do_signal_pending(NULL, regs);
do_signal(regs);
if (thread_info_flags & _TIF_NOTIFY_RESUME) {
clear_thread_flag(TIF_NOTIFY_RESUME);
tracehook_notify_resume(regs);
if (current->replacement_session_keyring)
key_replace_session_keyring();
}
}

2
arch/powerpc/kernel/signal.h
View File

@ -12,7 +12,7 @@
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
extern void do_signal(struct pt_regs *regs, unsigned long thread_info_flags);
extern void do_notify_resume(struct pt_regs *regs, unsigned long thread_info_flags);
extern void __user * get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
size_t frame_size, int is_32);

2
arch/powerpc/platforms/wsp/smp.c
View File

@ -71,7 +71,7 @@ int __devinit smp_a2_kick_cpu(int nr)
static int __init smp_a2_probe(void)
{
return cpus_weight(cpu_possible_map);
return num_possible_cpus();
}
static struct smp_ops_t a2_smp_ops = {

2
arch/s390/kernel/compat_wrapper.S
View File

@ -662,7 +662,7 @@ ENTRY(sys32_getresuid16_wrapper)
ENTRY(sys32_poll_wrapper)
llgtr %r2,%r2 # struct pollfd *
llgfr %r3,%r3 # unsigned int
lgfr %r4,%r4 # long
lgfr %r4,%r4 # int
jg sys_poll # branch to system call
ENTRY(sys32_setresgid16_wrapper)

5
arch/s390/kernel/process.c
View File

@ -76,7 +76,6 @@ static void default_idle(void)
if (test_thread_flag(TIF_MCCK_PENDING)) {
local_mcck_enable();
local_irq_enable();
s390_handle_mcck();
return;
}
trace_hardirqs_on();
@ -93,10 +92,12 @@ void cpu_idle(void)
for (;;) {
tick_nohz_idle_enter();
rcu_idle_enter();
while (!need_resched())
while (!need_resched() && !test_thread_flag(TIF_MCCK_PENDING))
default_idle();
rcu_idle_exit();
tick_nohz_idle_exit();
if (test_thread_flag(TIF_MCCK_PENDING))
s390_handle_mcck();
preempt_enable_no_resched();
schedule();
preempt_disable();

7
arch/s390/kernel/time.c
View File

@ -113,11 +113,14 @@ static void fixup_clock_comparator(unsigned long long delta)
static int s390_next_ktime(ktime_t expires,
struct clock_event_device *evt)
{
struct timespec ts;
u64 nsecs;
nsecs = ktime_to_ns(ktime_sub(expires, ktime_get_monotonic_offset()));
ts.tv_sec = ts.tv_nsec = 0;
monotonic_to_bootbased(&ts);
nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires));
do_div(nsecs, 125);
S390_lowcore.clock_comparator = TOD_UNIX_EPOCH + (nsecs << 9);
S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9);
set_clock_comparator(S390_lowcore.clock_comparator);
return 0;
}

2
arch/s390/mm/pgtable.c
View File

@ -574,7 +574,7 @@ static inline void page_table_free_pgste(unsigned long *table)
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
mp = (struct gmap_pgtable *) page->index;
BUG_ON(!list_empty(&mp->mapper));
pgtable_page_ctor(page);
pgtable_page_dtor(page);
atomic_set(&page->_mapcount, -1);
kfree(mp);
__free_page(page);

20
arch/sh/boards/board-sh7757lcr.c
View File

@ -168,6 +168,11 @@ static struct resource sh_eth_giga1_resources[] = {
.start = 0xfee00800,
.end = 0xfee00fff,
.flags = IORESOURCE_MEM,
}, {
/* TSU */
.start = 0xfee01800,
.end = 0xfee01fff,
.flags = IORESOURCE_MEM,
}, {
.start = 316,
.end = 316,
@ -210,20 +215,13 @@ static struct resource sh_mmcif_resources[] = {
},
};
static struct sh_mmcif_dma sh7757lcr_mmcif_dma = {
.chan_priv_tx = {
.slave_id = SHDMA_SLAVE_MMCIF_TX,
},
.chan_priv_rx = {
.slave_id = SHDMA_SLAVE_MMCIF_RX,
}
};
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.dma = &sh7757lcr_mmcif_dma,
.sup_pclk = 0x0f,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
MMC_CAP_NONREMOVABLE,
.ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
static struct platform_device sh_mmcif_device = {

1
arch/sh/boards/mach-ap325rxa/setup.c
View File

@ -22,6 +22,7 @@
#include <linux/i2c.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <media/ov772x.h>
#include <media/soc_camera.h>
#include <media/soc_camera_platform.h>

2
arch/sh/boards/mach-ecovec24/setup.c
View File

@ -29,9 +29,11 @@
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/sh_eth.h>
#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <sound/sh_fsi.h>
#include <media/sh_mobile_ceu.h>
#include <media/soc_camera.h>
#include <media/tw9910.h>
#include <media/mt9t112.h>
#include <asm/heartbeat.h>

1
arch/sh/boards/mach-kfr2r09/setup.c
View File

@ -22,6 +22,7 @@
#include <linux/input/sh_keysc.h>
#include <linux/i2c.h>
#include <linux/usb/r8a66597.h>
#include <linux/videodev2.h>
#include <media/rj54n1cb0c.h>
#include <media/soc_camera.h>
#include <media/sh_mobile_ceu.h>

2
arch/sh/boards/mach-migor/setup.c
View File

@ -21,9 +21,11 @@
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/gpio.h>
#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <media/ov772x.h>
#include <media/soc_camera.h>
#include <media/tw9910.h>
#include <asm/clock.h>
#include <asm/machvec.h>

1
arch/sh/boards/mach-se/7724/setup.c
View File

@ -24,6 +24,7 @@
#include <linux/input/sh_keysc.h>
#include <linux/usb/r8a66597.h>
#include <linux/sh_eth.h>
#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <media/sh_mobile_ceu.h>
#include <sound/sh_fsi.h>

2
arch/sh/drivers/pci/pci-sh7780.c
View File

@ -74,7 +74,7 @@ struct pci_errors {
{ SH4_PCIINT_MLCK, "master lock error" },
{ SH4_PCIINT_TABT, "target-target abort" },
{ SH4_PCIINT_TRET, "target retry time out" },
{ SH4_PCIINT_MFDE, "master function disable erorr" },
{ SH4_PCIINT_MFDE, "master function disable error" },
{ SH4_PCIINT_PRTY, "address parity error" },
{ SH4_PCIINT_SERR, "SERR" },
{ SH4_PCIINT_TWDP, "data parity error for target write" },

8
arch/sh/include/asm/device.h
View File

@ -3,9 +3,10 @@
*
* This file is released under the GPLv2
*/
#ifndef __ASM_SH_DEVICE_H
#define __ASM_SH_DEVICE_H
struct dev_archdata {
};
#include <asm-generic/device.h>
struct platform_device;
/* allocate contiguous memory chunk and fill in struct resource */
@ -14,5 +15,4 @@ int platform_resource_setup_memory(struct platform_device *pdev,
void plat_early_device_setup(void);
struct pdev_archdata {
};
#endif /* __ASM_SH_DEVICE_H */

2
arch/sh/kernel/cpu/sh4a/clock-sh7724.c
View File

@ -343,7 +343,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]),
CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
CLKDEV_DEV_ID("sh_fsi.0", &mstp_clks[HWBLK_SPU]),
CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]),
CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),

22
arch/sh/kernel/cpu/sh4a/setup-sh7757.c
View File

@ -133,7 +133,7 @@ static struct resource spi0_resources[] = {
[0] = {
.start = 0xfe002000,
.end = 0xfe0020ff,
.flags = IORESOURCE_MEM,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
},
[1] = {
.start = 86,
@ -661,6 +661,25 @@ static struct platform_device spi0_device = {
.resource = spi0_resources,
};
static struct resource spi1_resources[] = {
{
.start = 0xffd8ee70,
.end = 0xffd8eeff,
.flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
},
{
.start = 54,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device spi1_device = {
.name = "sh_spi",
.id = 1,
.num_resources = ARRAY_SIZE(spi1_resources),
.resource = spi1_resources,
};
static struct resource usb_ehci_resources[] = {
[0] = {
.start = 0xfe4f1000,
@ -720,6 +739,7 @@ static struct platform_device *sh7757_devices[] __initdata = {
&dma2_device,
&dma3_device,
&spi0_device,
&spi1_device,
&usb_ehci_device,
&usb_ohci_device,
};

2
arch/sh/kernel/smp.c
View File

@ -63,7 +63,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
mp_ops->prepare_cpus(max_cpus);
#ifndef CONFIG_HOTPLUG_CPU
init_cpu_present(&cpu_possible_map);
init_cpu_present(cpu_possible_mask);
#endif
}

2
arch/sh/kernel/topology.c
View File

@ -27,7 +27,7 @@ static cpumask_t cpu_coregroup_map(unsigned int cpu)
* Presently all SH-X3 SMP cores are multi-cores, so just keep it
* simple until we have a method for determining topology..
*/
return cpu_possible_map;
return *cpu_possible_mask;
}
const struct cpumask *cpu_coregroup_mask(unsigned int cpu)

2
arch/sh/mm/cache-sh2a.c
View File

@ -23,6 +23,7 @@
#define MAX_OCACHE_PAGES 32
#define MAX_ICACHE_PAGES 32
#ifdef CONFIG_CACHE_WRITEBACK
static void sh2a_flush_oc_line(unsigned long v, int way)
{
unsigned long addr = (v & 0x000007f0) | (way << 11);
@ -34,6 +35,7 @@ static void sh2a_flush_oc_line(unsigned long v, int way)
__raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr);
}
}
#endif
static void sh2a_invalidate_line(unsigned long cache_addr, unsigned long v)
{

53
arch/x86/include/asm/i387.h
View File

@ -29,10 +29,11 @@ extern unsigned int sig_xstate_size;
extern void fpu_init(void);
extern void mxcsr_feature_mask_init(void);
extern int init_fpu(struct task_struct *child);
extern void __math_state_restore(struct task_struct *);
extern void math_state_restore(void);
extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
DECLARE_PER_CPU(struct task_struct *, fpu_owner_task);
extern user_regset_active_fn fpregs_active, xfpregs_active;
extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
xstateregs_get;
@ -269,6 +270,16 @@ static inline int fpu_restore_checking(struct fpu *fpu)
static inline int restore_fpu_checking(struct task_struct *tsk)
{
/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
is pending. Clear the x87 state here by setting it to fixed
values. "m" is a random variable that should be in L1 */
alternative_input(
ASM_NOP8 ASM_NOP2,
"emms\n\t" /* clear stack tags */
"fildl %P[addr]", /* set F?P to defined value */
X86_FEATURE_FXSAVE_LEAK,
[addr] "m" (tsk->thread.fpu.has_fpu));
return fpu_restore_checking(&tsk->thread.fpu);
}
@ -279,19 +290,21 @@ static inline int restore_fpu_checking(struct task_struct *tsk)
*/
static inline int __thread_has_fpu(struct task_struct *tsk)
{
return tsk->thread.has_fpu;
return tsk->thread.fpu.has_fpu;
}
/* Must be paired with an 'stts' after! */
static inline void __thread_clear_has_fpu(struct task_struct *tsk)
{
tsk->thread.has_fpu = 0;
tsk->thread.fpu.has_fpu = 0;
percpu_write(fpu_owner_task, NULL);
}
/* Must be paired with a 'clts' before! */
static inline void __thread_set_has_fpu(struct task_struct *tsk)
{
tsk->thread.has_fpu = 1;
tsk->thread.fpu.has_fpu = 1;
percpu_write(fpu_owner_task, tsk);
}
/*
@ -336,30 +349,36 @@ typedef struct { int preload; } fpu_switch_t;
* We don't do that yet, so "fpu_lazy_restore()" always returns
* false, but some day..
*/
#define fpu_lazy_restore(tsk) (0)
#define fpu_lazy_state_intact(tsk) do { } while (0)
static inline int fpu_lazy_restore(struct task_struct *new, unsigned int cpu)
{
return new == percpu_read_stable(fpu_owner_task) &&
cpu == new->thread.fpu.last_cpu;
}
static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new)
static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct task_struct *new, int cpu)
{
fpu_switch_t fpu;
fpu.preload = tsk_used_math(new) && new->fpu_counter > 5;
if (__thread_has_fpu(old)) {
if (__save_init_fpu(old))
fpu_lazy_state_intact(old);
__thread_clear_has_fpu(old);
old->fpu_counter++;
if (!__save_init_fpu(old))
cpu = ~0;
old->thread.fpu.last_cpu = cpu;
old->thread.fpu.has_fpu = 0; /* But leave fpu_owner_task! */
/* Don't change CR0.TS if we just switch! */
if (fpu.preload) {
new->fpu_counter++;
__thread_set_has_fpu(new);
prefetch(new->thread.fpu.state);
} else
stts();
} else {
old->fpu_counter = 0;
old->thread.fpu.last_cpu = ~0;
if (fpu.preload) {
if (fpu_lazy_restore(new))
new->fpu_counter++;
if (fpu_lazy_restore(new, cpu))
fpu.preload = 0;
else
prefetch(new->thread.fpu.state);
@ -377,8 +396,10 @@ static inline fpu_switch_t switch_fpu_prepare(struct task_struct *old, struct ta
*/
static inline void switch_fpu_finish(struct task_struct *new, fpu_switch_t fpu)
{
if (fpu.preload)
__math_state_restore(new);
if (fpu.preload) {
if (unlikely(restore_fpu_checking(new)))
__thread_fpu_end(new);
}
}
/*
@ -451,8 +472,10 @@ static inline void kernel_fpu_begin(void)
__save_init_fpu(me);
__thread_clear_has_fpu(me);
/* We do 'stts()' in kernel_fpu_end() */
} else
} else {
percpu_write(fpu_owner_task, NULL);
clts();
}
}
static inline void kernel_fpu_end(void)

3
arch/x86/include/asm/processor.h
View File

@ -374,6 +374,8 @@ union thread_xstate {
};
struct fpu {
unsigned int last_cpu;
unsigned int has_fpu;
union thread_xstate *state;
};
@ -454,7 +456,6 @@ struct thread_struct {
unsigned long trap_no;
unsigned long error_code;
/* floating point and extended processor state */
unsigned long has_fpu;
struct fpu fpu;
#ifdef CONFIG_X86_32
/* Virtual 86 mode info */

5
arch/x86/kernel/cpu/common.c
View File

@ -1044,6 +1044,9 @@ DEFINE_PER_CPU(char *, irq_stack_ptr) =
DEFINE_PER_CPU(unsigned int, irq_count) = -1;
DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
/*
* Special IST stacks which the CPU switches to when it calls
* an IST-marked descriptor entry. Up to 7 stacks (hardware
@ -1111,6 +1114,8 @@ void debug_stack_reset(void)
DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
EXPORT_PER_CPU_SYMBOL(current_task);
DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
EXPORT_PER_CPU_SYMBOL(fpu_owner_task);
#ifdef CONFIG_CC_STACKPROTECTOR
DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);

3
arch/x86/kernel/process_32.c
View File

@ -214,6 +214,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
task_user_gs(p) = get_user_gs(regs);
p->fpu_counter = 0;
p->thread.io_bitmap_ptr = NULL;
tsk = current;
err = -ENOMEM;
@ -303,7 +304,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
/* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
fpu = switch_fpu_prepare(prev_p, next_p);
fpu = switch_fpu_prepare(prev_p, next_p, cpu);
/*
* Reload esp0.

3
arch/x86/kernel/process_64.c
View File

@ -286,6 +286,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
set_tsk_thread_flag(p, TIF_FORK);
p->fpu_counter = 0;
p->thread.io_bitmap_ptr = NULL;
savesegment(gs, p->thread.gsindex);
@ -388,7 +389,7 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
unsigned fsindex, gsindex;
fpu_switch_t fpu;
fpu = switch_fpu_prepare(prev_p, next_p);
fpu = switch_fpu_prepare(prev_p, next_p, cpu);
/*
* Reload esp0, LDT and the page table pointer:

40
arch/x86/kernel/traps.c
View File

@ -570,37 +570,6 @@ asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
{
}
/*
* This gets called with the process already owning the
* FPU state, and with CR0.TS cleared. It just needs to
* restore the FPU register state.
*/
void __math_state_restore(struct task_struct *tsk)
{
/* We need a safe address that is cheap to find and that is already
in L1. We've just brought in "tsk->thread.has_fpu", so use that */
#define safe_address (tsk->thread.has_fpu)
/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
is pending. Clear the x87 state here by setting it to fixed
values. safe_address is a random variable that should be in L1 */
alternative_input(
ASM_NOP8 ASM_NOP2,
"emms\n\t" /* clear stack tags */
"fildl %P[addr]", /* set F?P to defined value */
X86_FEATURE_FXSAVE_LEAK,
[addr] "m" (safe_address));
/*
* Paranoid restore. send a SIGSEGV if we fail to restore the state.
*/
if (unlikely(restore_fpu_checking(tsk))) {
__thread_fpu_end(tsk);
force_sig(SIGSEGV, tsk);
return;
}
}
/*
* 'math_state_restore()' saves the current math information in the
* old math state array, and gets the new ones from the current task
@ -631,7 +600,14 @@ void math_state_restore(void)
}
__thread_fpu_begin(tsk);
__math_state_restore(tsk);
/*
* Paranoid restore. send a SIGSEGV if we fail to restore the state.
*/
if (unlikely(restore_fpu_checking(tsk))) {
__thread_fpu_end(tsk);
force_sig(SIGSEGV, tsk);
return;
}
tsk->fpu_counter++;
}

2
drivers/block/nvme.c
View File

@ -41,6 +41,8 @@
#include <linux/types.h>
#include <linux/version.h>
#include <asm-generic/io-64-nonatomic-lo-hi.h>
#define NVME_Q_DEPTH 1024
#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))

2
drivers/cpuidle/Kconfig
View File

@ -1,7 +1,7 @@
config CPU_IDLE
bool "CPU idle PM support"
default ACPI
default y if ACPI || PPC_PSERIES
help
CPU idle is a generic framework for supporting software-controlled
idle processor power management. It includes modular cross-platform

15
drivers/edac/i3200_edac.c
View File

@ -15,6 +15,8 @@
#include <linux/io.h>
#include "edac_core.h"
#include <asm-generic/io-64-nonatomic-lo-hi.h>
#define I3200_REVISION "1.1"
#define EDAC_MOD_STR "i3200_edac"
@ -101,19 +103,6 @@ struct i3200_priv {
static int nr_channels;
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
{
const volatile u32 __iomem *p = addr;
u32 low, high;
low = readl(p);
high = readl(p + 1);
return low + ((u64)high << 32);
}
#endif
static int how_many_channels(struct pci_dev *pdev)
{
unsigned char capid0_8b; /* 8th byte of CAPID0 */

3
drivers/gpu/drm/exynos/exynos_drm_core.c
View File

@ -193,6 +193,9 @@ int exynos_drm_subdrv_register(struct exynos_drm_subdrv *subdrv)
return err;
}
/* setup possible_clones. */
exynos_drm_encoder_setup(drm_dev);
/*
* if any specific driver such as fimd or hdmi driver called
* exynos_drm_subdrv_register() later than drm_load(),

6
drivers/gpu/drm/exynos/exynos_drm_crtc.c
View File

@ -307,9 +307,6 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
*/
event->pipe = exynos_crtc->pipe;
list_add_tail(&event->base.link,
&dev_priv->pageflip_event_list);
ret = drm_vblank_get(dev, exynos_crtc->pipe);
if (ret) {
DRM_DEBUG("failed to acquire vblank counter\n");
@ -318,6 +315,9 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
goto out;
}
list_add_tail(&event->base.link,
&dev_priv->pageflip_event_list);
crtc->fb = fb;
ret = exynos_drm_crtc_update(crtc);
if (ret) {

26
drivers/gpu/drm/exynos/exynos_drm_drv.c
View File

@ -33,6 +33,7 @@
#include "exynos_drm_drv.h"
#include "exynos_drm_crtc.h"
#include "exynos_drm_encoder.h"
#include "exynos_drm_fbdev.h"
#include "exynos_drm_fb.h"
#include "exynos_drm_gem.h"
@ -99,6 +100,9 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags)
if (ret)
goto err_vblank;
/* setup possible_clones. */
exynos_drm_encoder_setup(dev);
/*
* create and configure fb helper and also exynos specific
* fbdev object.
@ -141,16 +145,21 @@ static int exynos_drm_unload(struct drm_device *dev)
}
static void exynos_drm_preclose(struct drm_device *dev,
struct drm_file *file_priv)
struct drm_file *file)
{
struct exynos_drm_private *dev_priv = dev->dev_private;
DRM_DEBUG_DRIVER("%s\n", __FILE__);
/*
* drm framework frees all events at release time,
* so private event list should be cleared.
*/
if (!list_empty(&dev_priv->pageflip_event_list))
INIT_LIST_HEAD(&dev_priv->pageflip_event_list);
}
static void exynos_drm_postclose(struct drm_device *dev, struct drm_file *file)
{
DRM_DEBUG_DRIVER("%s\n", __FILE__);
if (!file->driver_priv)
return;
kfree(file->driver_priv);
file->driver_priv = NULL;
}
static void exynos_drm_lastclose(struct drm_device *dev)
@ -195,6 +204,7 @@ static struct drm_driver exynos_drm_driver = {
.unload = exynos_drm_unload,
.preclose = exynos_drm_preclose,
.lastclose = exynos_drm_lastclose,
.postclose = exynos_drm_postclose,
.get_vblank_counter = drm_vblank_count,
.enable_vblank = exynos_drm_crtc_enable_vblank,
.disable_vblank = exynos_drm_crtc_disable_vblank,

34
drivers/gpu/drm/exynos/exynos_drm_encoder.c
View File

@ -195,6 +195,40 @@ static struct drm_encoder_funcs exynos_encoder_funcs = {
.destroy = exynos_drm_encoder_destroy,
};
static unsigned int exynos_drm_encoder_clones(struct drm_encoder *encoder)
{
struct drm_encoder *clone;
struct drm_device *dev = encoder->dev;
struct exynos_drm_encoder *exynos_encoder = to_exynos_encoder(encoder);
struct exynos_drm_display_ops *display_ops =
exynos_encoder->manager->display_ops;
unsigned int clone_mask = 0;
int cnt = 0;
list_for_each_entry(clone, &dev->mode_config.encoder_list, head) {
switch (display_ops->type) {
case EXYNOS_DISPLAY_TYPE_LCD:
case EXYNOS_DISPLAY_TYPE_HDMI:
clone_mask |= (1 << (cnt++));
break;
default:
continue;
}
}
return clone_mask;
}
void exynos_drm_encoder_setup(struct drm_device *dev)
{
struct drm_encoder *encoder;
DRM_DEBUG_KMS("%s\n", __FILE__);
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
encoder->possible_clones = exynos_drm_encoder_clones(encoder);
}
struct drm_encoder *
exynos_drm_encoder_create(struct drm_device *dev,
struct exynos_drm_manager *manager,

1
drivers/gpu/drm/exynos/exynos_drm_encoder.h
View File

@ -30,6 +30,7 @@
struct exynos_drm_manager;
void exynos_drm_encoder_setup(struct drm_device *dev);
struct drm_encoder *exynos_drm_encoder_create(struct drm_device *dev,
struct exynos_drm_manager *mgr,
unsigned int possible_crtcs);

70
drivers/gpu/drm/exynos/exynos_drm_fbdev.c
View File

@ -195,66 +195,6 @@ out:
return ret;
}
static bool
exynos_drm_fbdev_is_samefb(struct drm_framebuffer *fb,
struct drm_fb_helper_surface_size *sizes)
{
if (fb->width != sizes->surface_width)
return false;
if (fb->height != sizes->surface_height)
return false;
if (fb->bits_per_pixel != sizes->surface_bpp)
return false;
if (fb->depth != sizes->surface_depth)
return false;
return true;
}
static int exynos_drm_fbdev_recreate(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
struct drm_device *dev = helper->dev;
struct exynos_drm_fbdev *exynos_fbdev = to_exynos_fbdev(helper);
struct exynos_drm_gem_obj *exynos_gem_obj;
struct drm_framebuffer *fb = helper->fb;
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
unsigned long size;
DRM_DEBUG_KMS("%s\n", __FILE__);
if (exynos_drm_fbdev_is_samefb(fb, sizes))
return 0;
mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
mode_cmd.pitches[0] = sizes->surface_width * (sizes->surface_bpp >> 3);
mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
sizes->surface_depth);
if (exynos_fbdev->exynos_gem_obj)
exynos_drm_gem_destroy(exynos_fbdev->exynos_gem_obj);
if (fb->funcs->destroy)
fb->funcs->destroy(fb);
size = mode_cmd.pitches[0] * mode_cmd.height;
exynos_gem_obj = exynos_drm_gem_create(dev, size);
if (IS_ERR(exynos_gem_obj))
return PTR_ERR(exynos_gem_obj);
exynos_fbdev->exynos_gem_obj = exynos_gem_obj;
helper->fb = exynos_drm_framebuffer_init(dev, &mode_cmd,
&exynos_gem_obj->base);
if (IS_ERR_OR_NULL(helper->fb)) {
DRM_ERROR("failed to create drm framebuffer.\n");
return PTR_ERR(helper->fb);
}
return exynos_drm_fbdev_update(helper, helper->fb);
}
static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@ -262,6 +202,10 @@ static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper,
DRM_DEBUG_KMS("%s\n", __FILE__);
/*
* with !helper->fb, it means that this funcion is called first time
* and after that, the helper->fb would be used as clone mode.
*/
if (!helper->fb) {
ret = exynos_drm_fbdev_create(helper, sizes);
if (ret < 0) {
@ -274,12 +218,6 @@ static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper,
* because register_framebuffer() should be called.
*/
ret = 1;
} else {
ret = exynos_drm_fbdev_recreate(helper, sizes);
if (ret < 0) {
DRM_ERROR("failed to reconfigure fbdev\n");
return ret;
}
}
return ret;

7
drivers/gpu/drm/exynos/exynos_drm_fimd.c
View File

@ -604,7 +604,12 @@ static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
}
if (is_checked) {
drm_vblank_put(drm_dev, crtc);
/*
* call drm_vblank_put only in case that drm_vblank_get was
* called.
*/
if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
drm_vblank_put(drm_dev, crtc);
/*
* don't off vblank if vblank_disable_allowed is 1,

19
drivers/gpu/drm/exynos/exynos_mixer.c
View File

@ -712,7 +712,12 @@ static void mixer_finish_pageflip(struct drm_device *drm_dev, int crtc)
}
if (is_checked)
drm_vblank_put(drm_dev, crtc);
/*
* call drm_vblank_put only in case that drm_vblank_get was
* called.
*/
if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
drm_vblank_put(drm_dev, crtc);
spin_unlock_irqrestore(&drm_dev->event_lock, flags);
}
@ -779,15 +784,15 @@ static void mixer_win_reset(struct mixer_context *ctx)
mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
MXR_STATUS_BURST_MASK);
/* setting default layer priority: layer1 > video > layer0
/* setting default layer priority: layer1 > layer0 > video
* because typical usage scenario would be
* layer1 - OSD
* layer0 - framebuffer
* video - video overlay
* layer1 - OSD
*/
val = MXR_LAYER_CFG_GRP0_VAL(1);
val |= MXR_LAYER_CFG_VP_VAL(2);
val |= MXR_LAYER_CFG_GRP1_VAL(3);
val = MXR_LAYER_CFG_GRP1_VAL(3);
val |= MXR_LAYER_CFG_GRP0_VAL(2);
val |= MXR_LAYER_CFG_VP_VAL(1);
mixer_reg_write(res, MXR_LAYER_CFG, val);
/* setting background color */
@ -1044,7 +1049,7 @@ static int mixer_remove(struct platform_device *pdev)
platform_get_drvdata(pdev);
struct mixer_context *ctx = (struct mixer_context *)drm_hdmi_ctx->ctx;
dev_info(dev, "remove sucessful\n");
dev_info(dev, "remove successful\n");
mixer_resource_poweroff(ctx);
mixer_resources_cleanup(ctx);

15
drivers/gpu/drm/i915/i915_reg.h
View File

@ -3028,6 +3028,20 @@
#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
#define DISP_FBC_WM_DIS (1<<15)
/* GEN7 chicken */
#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
#define GEN7_L3CNTLREG1 0xB01C
#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
/* WaCatErrorRejectionIssue */
#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
/* PCH */
/* south display engine interrupt */
@ -3618,6 +3632,7 @@
#define GT_FIFO_NUM_RESERVED_ENTRIES 20
#define GEN6_UCGCTL2 0x9404
# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)

24
drivers/gpu/drm/i915/intel_display.c
View File

@ -8184,8 +8184,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
if (intel_enable_rc6(dev_priv->dev))
rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
GEN6_RC_CTL_RC6_ENABLE;
rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
(IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
I915_WRITE(GEN6_RC_CONTROL,
rc6_mask |
@ -8463,12 +8463,32 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
I915_WRITE(WM2_LP_ILK, 0);
I915_WRITE(WM1_LP_ILK, 0);
/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating workaround.
*/
I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
I915_WRITE(IVB_CHICKEN3,
CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
CHICKEN3_DGMG_DONE_FIX_DISABLE);
/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
I915_WRITE(GEN7_L3CNTLREG1,
GEN7_WA_FOR_GEN7_L3_CONTROL);
I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
GEN7_WA_L3_CHICKEN_MODE);
/* This is required by WaCatErrorRejectionIssue */
I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
for_each_pipe(pipe) {
I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) |

1
drivers/gpu/drm/radeon/evergreen.c
View File

@ -3223,6 +3223,7 @@ int evergreen_resume(struct radeon_device *rdev)
r = evergreen_startup(rdev);
if (r) {
DRM_ERROR("evergreen startup failed on resume\n");
rdev->accel_working = false;
return r;
}

1
drivers/gpu/drm/radeon/ni.c
View File

@ -1547,6 +1547,7 @@ int cayman_resume(struct radeon_device *rdev)
r = cayman_startup(rdev);
if (r) {
DRM_ERROR("cayman startup failed on resume\n");
rdev->accel_working = false;
return r;
}
return r;

8
drivers/gpu/drm/radeon/r100.c
View File

@ -3928,6 +3928,8 @@ static int r100_startup(struct radeon_device *rdev)
int r100_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCI)
r100_pci_gart_disable(rdev);
@ -3947,7 +3949,11 @@ int r100_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return r100_startup(rdev);
r = r100_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int r100_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/r300.c
View File

@ -1431,6 +1431,8 @@ static int r300_startup(struct radeon_device *rdev)
int r300_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCIE)
rv370_pcie_gart_disable(rdev);
@ -1452,7 +1454,11 @@ int r300_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return r300_startup(rdev);
r = r300_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int r300_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/r420.c
View File

@ -291,6 +291,8 @@ static int r420_startup(struct radeon_device *rdev)
int r420_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCIE)
rv370_pcie_gart_disable(rdev);
@ -316,7 +318,11 @@ int r420_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return r420_startup(rdev);
r = r420_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int r420_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/r520.c
View File

@ -218,6 +218,8 @@ static int r520_startup(struct radeon_device *rdev)
int r520_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCIE)
rv370_pcie_gart_disable(rdev);
@ -237,7 +239,11 @@ int r520_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return r520_startup(rdev);
r = r520_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int r520_init(struct radeon_device *rdev)

1
drivers/gpu/drm/radeon/r600.c
View File

@ -2529,6 +2529,7 @@ int r600_resume(struct radeon_device *rdev)
r = r600_startup(rdev);
if (r) {
DRM_ERROR("r600 startup failed on resume\n");
rdev->accel_working = false;
return r;
}

3
drivers/gpu/drm/radeon/radeon_atombios.c
View File

@ -3020,6 +3020,9 @@ radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
uint32_t bios_2_scratch;
if (ASIC_IS_DCE4(rdev))
return;
if (rdev->family >= CHIP_R600)
bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
else

4
drivers/gpu/drm/radeon/radeon_cs.c
View File

@ -453,6 +453,10 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
int r;
radeon_mutex_lock(&rdev->cs_mutex);
if (!rdev->accel_working) {
radeon_mutex_unlock(&rdev->cs_mutex);
return -EBUSY;
}
/* initialize parser */
memset(&parser, 0, sizeof(struct radeon_cs_parser));
parser.filp = filp;

7
drivers/gpu/drm/radeon/radeon_ring.c
View File

@ -500,8 +500,11 @@ static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
int radeon_debugfs_ring_init(struct radeon_device *rdev)
{
#if defined(CONFIG_DEBUG_FS)
return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
ARRAY_SIZE(radeon_debugfs_ring_info_list));
if (rdev->family >= CHIP_CAYMAN)
return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
ARRAY_SIZE(radeon_debugfs_ring_info_list));
else
return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list, 1);
#else
return 0;
#endif

8
drivers/gpu/drm/radeon/rs400.c
View File

@ -442,6 +442,8 @@ static int rs400_startup(struct radeon_device *rdev)
int rs400_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
rs400_gart_disable(rdev);
/* Resume clock before doing reset */
@ -462,7 +464,11 @@ int rs400_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return rs400_startup(rdev);
r = rs400_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int rs400_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/rs600.c
View File

@ -876,6 +876,8 @@ static int rs600_startup(struct radeon_device *rdev)
int rs600_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
rs600_gart_disable(rdev);
/* Resume clock before doing reset */
@ -894,7 +896,11 @@ int rs600_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return rs600_startup(rdev);
r = rs600_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int rs600_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/rs690.c
View File

@ -659,6 +659,8 @@ static int rs690_startup(struct radeon_device *rdev)
int rs690_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
rs400_gart_disable(rdev);
/* Resume clock before doing reset */
@ -677,7 +679,11 @@ int rs690_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return rs690_startup(rdev);
r = rs690_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int rs690_suspend(struct radeon_device *rdev)

8
drivers/gpu/drm/radeon/rv515.c
View File

@ -424,6 +424,8 @@ static int rv515_startup(struct radeon_device *rdev)
int rv515_resume(struct radeon_device *rdev)
{
int r;
/* Make sur GART are not working */
if (rdev->flags & RADEON_IS_PCIE)
rv370_pcie_gart_disable(rdev);
@ -443,7 +445,11 @@ int rv515_resume(struct radeon_device *rdev)
radeon_surface_init(rdev);
rdev->accel_working = true;
return rv515_startup(rdev);
r = rv515_startup(rdev);
if (r) {
rdev->accel_working = false;
}
return r;
}
int rv515_suspend(struct radeon_device *rdev)

1
drivers/gpu/drm/radeon/rv770.c
View File

@ -1139,6 +1139,7 @@ int rv770_resume(struct radeon_device *rdev)
r = rv770_startup(rdev);
if (r) {
DRM_ERROR("r600 startup failed on resume\n");
rdev->accel_working = false;
return r;
}

3
drivers/hwmon/ads1015.c
View File

@ -271,7 +271,7 @@ static int ads1015_probe(struct i2c_client *client,
continue;
err = device_create_file(&client->dev, &ads1015_in[k].dev_attr);
if (err)
goto exit_free;
goto exit_remove;
}
data->hwmon_dev = hwmon_device_register(&client->dev);
@ -285,7 +285,6 @@ static int ads1015_probe(struct i2c_client *client,
exit_remove:
for (k = 0; k < ADS1015_CHANNELS; ++k)
device_remove_file(&client->dev, &ads1015_in[k].dev_attr);
exit_free:
kfree(data);
exit:
return err;

7
drivers/hwmon/f75375s.c
View File

@ -340,8 +340,6 @@ static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val)
fanmode |= (1 << F75387_FAN_MANU_MODE(nr));
fanmode |= (1 << F75387_FAN_DUTY_MODE(nr));
data->pwm[nr] = 255;
f75375_write8(client, F75375_REG_FAN_PWM_DUTY(nr),
data->pwm[nr]);
break;
case 1: /* PWM */
fanmode |= (1 << F75387_FAN_MANU_MODE(nr));
@ -361,8 +359,6 @@ static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val)
case 0: /* full speed */
fanmode |= (3 << FAN_CTRL_MODE(nr));
data->pwm[nr] = 255;
f75375_write8(client, F75375_REG_FAN_PWM_DUTY(nr),
data->pwm[nr]);
break;
case 1: /* PWM */
fanmode |= (3 << FAN_CTRL_MODE(nr));
@ -377,6 +373,9 @@ static int set_pwm_enable_direct(struct i2c_client *client, int nr, int val)
f75375_write8(client, F75375_REG_FAN_TIMER, fanmode);
data->pwm_enable[nr] = val;
if (val == 0)
f75375_write8(client, F75375_REG_FAN_PWM_DUTY(nr),
data->pwm[nr]);
return 0;
}

22
drivers/hwmon/max6639.c
View File

@ -72,8 +72,8 @@ static unsigned short normal_i2c[] = { 0x2c, 0x2e, 0x2f, I2C_CLIENT_END };
static const int rpm_ranges[] = { 2000, 4000, 8000, 16000 };
#define FAN_FROM_REG(val, div, rpm_range) ((val) == 0 ? -1 : \
(val) == 255 ? 0 : (rpm_ranges[rpm_range] * 30) / ((div + 1) * (val)))
#define FAN_FROM_REG(val, rpm_range) ((val) == 0 || (val) == 255 ? \
0 : (rpm_ranges[rpm_range] * 30) / (val))
#define TEMP_LIMIT_TO_REG(val) SENSORS_LIMIT((val) / 1000, 0, 255)
/*
@ -333,7 +333,7 @@ static ssize_t show_fan_input(struct device *dev,
return PTR_ERR(data);
return sprintf(buf, "%d\n", FAN_FROM_REG(data->fan[attr->index],
data->ppr, data->rpm_range));
data->rpm_range));
}
static ssize_t show_alarm(struct device *dev,
@ -429,9 +429,9 @@ static int max6639_init_client(struct i2c_client *client)
struct max6639_data *data = i2c_get_clientdata(client);
struct max6639_platform_data *max6639_info =
client->dev.platform_data;
int i = 0;
int i;
int rpm_range = 1; /* default: 4000 RPM */
int err = 0;
int err;
/* Reset chip to default values, see below for GCONFIG setup */
err = i2c_smbus_write_byte_data(client, MAX6639_REG_GCONFIG,
@ -446,11 +446,6 @@ static int max6639_init_client(struct i2c_client *client)
else
data->ppr = 2;
data->ppr -= 1;
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_PPR(i),
data->ppr << 5);
if (err)
goto exit;
if (max6639_info)
rpm_range = rpm_range_to_reg(max6639_info->rpm_range);
@ -458,6 +453,13 @@ static int max6639_init_client(struct i2c_client *client)
for (i = 0; i < 2; i++) {
/* Set Fan pulse per revolution */
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_PPR(i),
data->ppr << 6);
if (err)
goto exit;
/* Fans config PWM, RPM */
err = i2c_smbus_write_byte_data(client,
MAX6639_REG_FAN_CONFIG1(i),

2
drivers/hwmon/pmbus/max34440.c
View File

@ -82,7 +82,7 @@ static int max34440_write_word_data(struct i2c_client *client, int page,
case PMBUS_VIRT_RESET_TEMP_HISTORY:
ret = pmbus_write_word_data(client, page,
MAX34440_MFR_TEMPERATURE_PEAK,
0xffff);
0x8000);
break;
default:
ret = -ENODATA;

4
drivers/media/radio/wl128x/Kconfig
View File

@ -4,8 +4,8 @@
menu "Texas Instruments WL128x FM driver (ST based)"
config RADIO_WL128X
tristate "Texas Instruments WL128x FM Radio"
depends on VIDEO_V4L2 && RFKILL
select TI_ST if NET && GPIOLIB
depends on VIDEO_V4L2 && RFKILL && GPIOLIB
select TI_ST if NET
help
Choose Y here if you have this FM radio chip.

26
drivers/media/rc/imon.c
View File

@ -47,7 +47,7 @@
#define MOD_AUTHOR "Jarod Wilson <jarod@wilsonet.com>"
#define MOD_DESC "Driver for SoundGraph iMON MultiMedia IR/Display"
#define MOD_NAME "imon"
#define MOD_VERSION "0.9.3"
#define MOD_VERSION "0.9.4"
#define DISPLAY_MINOR_BASE 144
#define DEVICE_NAME "lcd%d"
@ -1658,9 +1658,17 @@ static void usb_rx_callback_intf0(struct urb *urb)
return;
ictx = (struct imon_context *)urb->context;
if (!ictx || !ictx->dev_present_intf0)
if (!ictx)
return;
/*
* if we get a callback before we're done configuring the hardware, we
* can't yet process the data, as there's nowhere to send it, but we
* still need to submit a new rx URB to avoid wedging the hardware
*/
if (!ictx->dev_present_intf0)
goto out;
switch (urb->status) {
case -ENOENT: /* usbcore unlink successful! */
return;
@ -1678,6 +1686,7 @@ static void usb_rx_callback_intf0(struct urb *urb)
break;
}
out:
usb_submit_urb(ictx->rx_urb_intf0, GFP_ATOMIC);
}
@ -1690,9 +1699,17 @@ static void usb_rx_callback_intf1(struct urb *urb)
return;
ictx = (struct imon_context *)urb->context;
if (!ictx || !ictx->dev_present_intf1)
if (!ictx)
return;
/*
* if we get a callback before we're done configuring the hardware, we
* can't yet process the data, as there's nowhere to send it, but we
* still need to submit a new rx URB to avoid wedging the hardware
*/
if (!ictx->dev_present_intf1)
goto out;
switch (urb->status) {
case -ENOENT: /* usbcore unlink successful! */
return;
@ -1710,6 +1727,7 @@ static void usb_rx_callback_intf1(struct urb *urb)
break;
}
out:
usb_submit_urb(ictx->rx_urb_intf1, GFP_ATOMIC);
}
@ -2242,7 +2260,7 @@ find_endpoint_failed:
mutex_unlock(&ictx->lock);
usb_free_urb(rx_urb);
rx_urb_alloc_failed:
dev_err(ictx->dev, "unable to initialize intf0, err %d\n", ret);
dev_err(ictx->dev, "unable to initialize intf1, err %d\n", ret);
return NULL;
}

20
drivers/media/video/hdpvr/hdpvr-core.c
View File

@ -154,10 +154,20 @@ static int device_authorization(struct hdpvr_device *dev)
}
#endif
v4l2_info(&dev->v4l2_dev, "firmware version 0x%x dated %s\n",
dev->usbc_buf[1], &dev->usbc_buf[2]);
dev->fw_ver = dev->usbc_buf[1];
switch (dev->usbc_buf[1]) {
v4l2_info(&dev->v4l2_dev, "firmware version 0x%x dated %s\n",
dev->fw_ver, &dev->usbc_buf[2]);
if (dev->fw_ver > 0x15) {
dev->options.brightness = 0x80;
dev->options.contrast = 0x40;
dev->options.hue = 0xf;
dev->options.saturation = 0x40;
dev->options.sharpness = 0x80;
}
switch (dev->fw_ver) {
case HDPVR_FIRMWARE_VERSION:
dev->flags &= ~HDPVR_FLAG_AC3_CAP;
break;
@ -169,7 +179,7 @@ static int device_authorization(struct hdpvr_device *dev)
default:
v4l2_info(&dev->v4l2_dev, "untested firmware, the driver might"
" not work.\n");
if (dev->usbc_buf[1] >= HDPVR_FIRMWARE_VERSION_AC3)
if (dev->fw_ver >= HDPVR_FIRMWARE_VERSION_AC3)
dev->flags |= HDPVR_FLAG_AC3_CAP;
else
dev->flags &= ~HDPVR_FLAG_AC3_CAP;
@ -270,6 +280,8 @@ static const struct hdpvr_options hdpvr_default_options = {
.bitrate_mode = HDPVR_CONSTANT,
.gop_mode = HDPVR_SIMPLE_IDR_GOP,
.audio_codec = V4L2_MPEG_AUDIO_ENCODING_AAC,
/* original picture controls for firmware version <= 0x15 */
/* updated in device_authorization() for newer firmware */
.brightness = 0x86,
.contrast = 0x80,
.hue = 0x80,

46
drivers/media/video/hdpvr/hdpvr-video.c
View File

@ -283,12 +283,13 @@ static int hdpvr_start_streaming(struct hdpvr_device *dev)
hdpvr_config_call(dev, CTRL_START_STREAMING_VALUE, 0x00);
dev->status = STATUS_STREAMING;
INIT_WORK(&dev->worker, hdpvr_transmit_buffers);
queue_work(dev->workqueue, &dev->worker);
v4l2_dbg(MSG_BUFFER, hdpvr_debug, &dev->v4l2_dev,
"streaming started\n");
dev->status = STATUS_STREAMING;
return 0;
}
@ -722,21 +723,39 @@ static const s32 supported_v4l2_ctrls[] = {
};
static int fill_queryctrl(struct hdpvr_options *opt, struct v4l2_queryctrl *qc,
int ac3)
int ac3, int fw_ver)
{
int err;
if (fw_ver > 0x15) {
switch (qc->id) {
case V4L2_CID_BRIGHTNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_CONTRAST:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x40);
case V4L2_CID_SATURATION:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x40);
case V4L2_CID_HUE:
return v4l2_ctrl_query_fill(qc, 0x0, 0x1e, 1, 0xf);
case V4L2_CID_SHARPNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
}
} else {
switch (qc->id) {
case V4L2_CID_BRIGHTNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x86);
case V4L2_CID_CONTRAST:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_SATURATION:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_HUE:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_SHARPNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
}
}
switch (qc->id) {
case V4L2_CID_BRIGHTNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x86);
case V4L2_CID_CONTRAST:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_SATURATION:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_HUE:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_SHARPNESS:
return v4l2_ctrl_query_fill(qc, 0x0, 0xff, 1, 0x80);
case V4L2_CID_MPEG_AUDIO_ENCODING:
return v4l2_ctrl_query_fill(
qc, V4L2_MPEG_AUDIO_ENCODING_AAC,
@ -794,7 +813,8 @@ static int vidioc_queryctrl(struct file *file, void *private_data,
if (qc->id == supported_v4l2_ctrls[i])
return fill_queryctrl(&dev->options, qc,
dev->flags & HDPVR_FLAG_AC3_CAP);
dev->flags & HDPVR_FLAG_AC3_CAP,
dev->fw_ver);
if (qc->id < supported_v4l2_ctrls[i])
break;

1
drivers/media/video/hdpvr/hdpvr.h
View File

@ -113,6 +113,7 @@ struct hdpvr_device {
/* usb control transfer buffer and lock */
struct mutex usbc_mutex;
u8 *usbc_buf;
u8 fw_ver;
};
static inline struct hdpvr_device *to_hdpvr_dev(struct v4l2_device *v4l2_dev)

2
drivers/media/video/omap3isp/ispccdc.c
View File

@ -1407,7 +1407,7 @@ static int __ccdc_handle_stopping(struct isp_ccdc_device *ccdc, u32 event)
static void ccdc_hs_vs_isr(struct isp_ccdc_device *ccdc)
{
struct isp_pipeline *pipe = to_isp_pipeline(&ccdc->subdev.entity);
struct video_device *vdev = &ccdc->subdev.devnode;
struct video_device *vdev = ccdc->subdev.devnode;
struct v4l2_event event;
memset(&event, 0, sizeof(event));

2
drivers/net/ethernet/mellanox/mlx4/fw.c
View File

@ -685,7 +685,7 @@ int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
return err;
}
static int mlx4_QUERY_PORT(struct mlx4_dev *dev, void *ptr, u8 port)
int mlx4_QUERY_PORT(struct mlx4_dev *dev, void *ptr, u8 port)
{
struct mlx4_cmd_mailbox *outbox = ptr;

12
drivers/net/ethernet/mellanox/mlx4/mr.c
View File

@ -304,7 +304,7 @@ static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox
MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
}
static int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align,
int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align,
u32 *base_mridx)
{
struct mlx4_priv *priv = mlx4_priv(dev);
@ -320,14 +320,14 @@ static int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align,
}
EXPORT_SYMBOL_GPL(mlx4_mr_reserve_range);
static void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt)
void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt)
{
struct mlx4_priv *priv = mlx4_priv(dev);
mlx4_bitmap_free_range(&priv->mr_table.mpt_bitmap, base_mridx, cnt);
}
EXPORT_SYMBOL_GPL(mlx4_mr_release_range);
static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd,
u64 iova, u64 size, u32 access, int npages,
int page_shift, struct mlx4_mr *mr)
{
@ -457,7 +457,7 @@ int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
}
EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
static void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr)
{
int err;
@ -852,7 +852,7 @@ err_free:
}
EXPORT_SYMBOL_GPL(mlx4_fmr_alloc);
static int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx,
int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx,
u32 pd, u32 access, int max_pages,
int max_maps, u8 page_shift, struct mlx4_fmr *fmr)
{
@ -954,7 +954,7 @@ int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
}
EXPORT_SYMBOL_GPL(mlx4_fmr_free);
static int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr)
{
if (fmr->maps)
return -EBUSY;

15
drivers/platform/x86/ibm_rtl.c
View File

@ -33,6 +33,8 @@
#include <linux/mutex.h>
#include <asm/bios_ebda.h>
#include <asm-generic/io-64-nonatomic-lo-hi.h>
static bool force;
module_param(force, bool, 0);
MODULE_PARM_DESC(force, "Force driver load, ignore DMI data");
@ -83,19 +85,6 @@ static void __iomem *rtl_cmd_addr;
static u8 rtl_cmd_type;
static u8 rtl_cmd_width;
#ifndef readq
static inline __u64 readq(const volatile void __iomem *addr)
{
const volatile u32 __iomem *p = addr;
u32 low, high;
low = readl(p);
high = readl(p + 1);
return low + ((u64)high << 32);
}
#endif
static void __iomem *rtl_port_map(phys_addr_t addr, unsigned long len)
{
if (rtl_cmd_type == RTL_ADDR_TYPE_MMIO)

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