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tpmdd updates for Linux v5.20
-----BEGIN PGP SIGNATURE----- iIgEABYKADAWIQRE6pSOnaBC00OEHEIaerohdGur0gUCYurhKxIcamFya2tvQGtl cm5lbC5vcmcACgkQGnq6IXRrq9LE8wD7BLzsrUxA60RVdGW8qLgcZoJEt2GHe+FT kZ1LlYoNGDsA/ixBGFPS4P1aEPnrKId3tdVxa5uJ7yRVGCdN665+dukE =fCoD -----END PGP SIGNATURE----- Merge tag 'tpmdd-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd Pull tpm updates from Jarkko Sakkinen: "Mostly TPM and also few keyring fixes" * tag 'tpmdd-next-v5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd: tpm: Add check for Failure mode for TPM2 modules tpm: eventlog: Fix section mismatch for DEBUG_SECTION_MISMATCH tpm: fix platform_no_drv_owner.cocci warning KEYS: asymmetric: enforce SM2 signature use pkey algo pkcs7: support EC-RDSA/streebog in SignerInfo pkcs7: parser support SM2 and SM3 algorithms combination sign-file: Fix confusing error messages X.509: Support parsing certificate using SM2 algorithm tpm: Add tpm_tis_i2c backend for tpm_tis_core tpm: Add tpm_tis_verify_crc to the tpm_tis_phy_ops protocol layer dt-bindings: trivial-devices: Add Infineon SLB9673 TPM tpm: Add upgrade/reduced mode support for TPM1.2 modules
This commit is contained in:
Linus Torvalds
commit
f20c95b46b
@ -141,6 +141,8 @@ properties:
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- infineon,slb9635tt
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# Infineon SLB9645 I2C TPM (new protocol, max 400khz)
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- infineon,slb9645tt
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# Infineon SLB9673 I2C TPM 2.0
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- infineon,slb9673
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# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
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- infineon,tlv493d-a1b6
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# Infineon Multi-phase Digital VR Controller xdpe11280
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@ -248,6 +248,15 @@ int pkcs7_sig_note_digest_algo(void *context, size_t hdrlen,
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case OID_sha224:
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ctx->sinfo->sig->hash_algo = "sha224";
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break;
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case OID_sm3:
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ctx->sinfo->sig->hash_algo = "sm3";
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break;
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case OID_gost2012Digest256:
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ctx->sinfo->sig->hash_algo = "streebog256";
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break;
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case OID_gost2012Digest512:
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ctx->sinfo->sig->hash_algo = "streebog512";
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break;
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default:
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printk("Unsupported digest algo: %u\n", ctx->last_oid);
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return -ENOPKG;
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@ -277,6 +286,15 @@ int pkcs7_sig_note_pkey_algo(void *context, size_t hdrlen,
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ctx->sinfo->sig->pkey_algo = "ecdsa";
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ctx->sinfo->sig->encoding = "x962";
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break;
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case OID_SM2_with_SM3:
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ctx->sinfo->sig->pkey_algo = "sm2";
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ctx->sinfo->sig->encoding = "raw";
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break;
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case OID_gost2012PKey256:
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case OID_gost2012PKey512:
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ctx->sinfo->sig->pkey_algo = "ecrdsa";
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ctx->sinfo->sig->encoding = "raw";
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break;
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default:
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printk("Unsupported pkey algo: %u\n", ctx->last_oid);
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return -ENOPKG;
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@ -304,6 +304,10 @@ static int cert_sig_digest_update(const struct public_key_signature *sig,
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BUG_ON(!sig->data);
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/* SM2 signatures always use the SM3 hash algorithm */
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if (!sig->hash_algo || strcmp(sig->hash_algo, "sm3") != 0)
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return -EINVAL;
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ret = sm2_compute_z_digest(tfm_pkey, SM2_DEFAULT_USERID,
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SM2_DEFAULT_USERID_LEN, dgst);
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if (ret)
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@ -414,8 +418,7 @@ int public_key_verify_signature(const struct public_key *pkey,
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if (ret)
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goto error_free_key;
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if (sig->pkey_algo && strcmp(sig->pkey_algo, "sm2") == 0 &&
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sig->data_size) {
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if (strcmp(pkey->pkey_algo, "sm2") == 0 && sig->data_size) {
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ret = cert_sig_digest_update(sig, tfm);
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if (ret)
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goto error_free_key;
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@ -508,6 +508,9 @@ int x509_extract_key_data(void *context, size_t hdrlen,
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case OID_gost2012PKey512:
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ctx->cert->pub->pkey_algo = "ecrdsa";
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break;
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case OID_sm2:
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ctx->cert->pub->pkey_algo = "sm2";
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break;
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case OID_id_ecPublicKey:
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if (parse_OID(ctx->params, ctx->params_size, &oid) != 0)
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return -EBADMSG;
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@ -74,6 +74,18 @@ config TCG_TIS_SPI_CR50
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If you have a H1 secure module running Cr50 firmware on SPI bus,
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say Yes and it will be accessible from within Linux.
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config TCG_TIS_I2C
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tristate "TPM Interface Specification 1.3 Interface / TPM 2.0 FIFO Interface - (I2C - generic)"
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depends on I2C
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select CRC_CCITT
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select TCG_TIS_CORE
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help
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If you have a TPM security chip, compliant with the TCG TPM PTP
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(I2C interface) specification and connected to an I2C bus master,
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say Yes and it will be accessible from within Linux.
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To compile this driver as a module, choose M here;
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the module will be called tpm_tis_i2c.
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config TCG_TIS_SYNQUACER
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tristate "TPM Interface Specification 1.2 Interface / TPM 2.0 FIFO Interface (MMIO - SynQuacer)"
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depends on ARCH_SYNQUACER || COMPILE_TEST
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@ -29,6 +29,7 @@ tpm_tis_spi-$(CONFIG_TCG_TIS_SPI_CR50) += tpm_tis_spi_cr50.o
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obj-$(CONFIG_TCG_TIS_I2C_CR50) += tpm_tis_i2c_cr50.o
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obj-$(CONFIG_TCG_TIS_I2C) += tpm_tis_i2c.o
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obj-$(CONFIG_TCG_TIS_I2C_ATMEL) += tpm_i2c_atmel.o
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obj-$(CONFIG_TCG_TIS_I2C_INFINEON) += tpm_i2c_infineon.o
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obj-$(CONFIG_TCG_TIS_I2C_NUVOTON) += tpm_i2c_nuvoton.o
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@ -55,6 +55,7 @@ enum tpm_addr {
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#define TPM_WARN_DOING_SELFTEST 0x802
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#define TPM_ERR_DEACTIVATED 0x6
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#define TPM_ERR_DISABLED 0x7
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#define TPM_ERR_FAILEDSELFTEST 0x1C
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#define TPM_ERR_INVALID_POSTINIT 38
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#define TPM_TAG_RQU_COMMAND 193
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@ -709,7 +709,12 @@ int tpm1_auto_startup(struct tpm_chip *chip)
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if (rc)
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goto out;
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rc = tpm1_do_selftest(chip);
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if (rc) {
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if (rc == TPM_ERR_FAILEDSELFTEST) {
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dev_warn(&chip->dev, "TPM self test failed, switching to the firmware upgrade mode\n");
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/* A TPM in this state possibly allows or needs a firmware upgrade */
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chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
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return 0;
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} else if (rc) {
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dev_err(&chip->dev, "TPM self test failed\n");
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goto out;
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}
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@ -752,6 +752,12 @@ int tpm2_auto_startup(struct tpm_chip *chip)
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}
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rc = tpm2_get_cc_attrs_tbl(chip);
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if (rc == TPM2_RC_FAILURE || (rc < 0 && rc != -ENOMEM)) {
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dev_info(&chip->dev,
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"TPM in field failure mode, requires firmware upgrade\n");
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chip->flags |= TPM_CHIP_FLAG_FIRMWARE_UPGRADE;
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rc = 0;
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}
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out:
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/*
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@ -289,6 +289,7 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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int size = 0;
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int status;
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u32 expected;
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int rc;
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if (count < TPM_HEADER_SIZE) {
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size = -EIO;
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@ -328,6 +329,13 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
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goto out;
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}
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rc = tpm_tis_verify_crc(priv, (size_t)size, buf);
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if (rc < 0) {
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dev_err(&chip->dev, "CRC mismatch for response.\n");
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size = rc;
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goto out;
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}
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out:
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tpm_tis_ready(chip);
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return size;
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@ -443,6 +451,12 @@ static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len)
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if (rc < 0)
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return rc;
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rc = tpm_tis_verify_crc(priv, len, buf);
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if (rc < 0) {
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dev_err(&chip->dev, "CRC mismatch for command.\n");
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return rc;
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}
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/* go and do it */
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rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO);
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if (rc < 0)
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@ -121,6 +121,8 @@ struct tpm_tis_phy_ops {
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u8 *result, enum tpm_tis_io_mode mode);
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int (*write_bytes)(struct tpm_tis_data *data, u32 addr, u16 len,
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const u8 *value, enum tpm_tis_io_mode mode);
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int (*verify_crc)(struct tpm_tis_data *data, size_t len,
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const u8 *value);
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};
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static inline int tpm_tis_read_bytes(struct tpm_tis_data *data, u32 addr,
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@ -188,6 +190,14 @@ static inline int tpm_tis_write32(struct tpm_tis_data *data, u32 addr,
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return rc;
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}
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static inline int tpm_tis_verify_crc(struct tpm_tis_data *data, size_t len,
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const u8 *value)
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{
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if (!data->phy_ops->verify_crc)
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return 0;
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return data->phy_ops->verify_crc(data, len, value);
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}
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static inline bool is_bsw(void)
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{
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#ifdef CONFIG_X86
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390
drivers/char/tpm/tpm_tis_i2c.c
Normal file
390
drivers/char/tpm/tpm_tis_i2c.c
Normal file
@ -0,0 +1,390 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014-2021 Nuvoton Technology corporation
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* Copyright (C) 2019-2022 Infineon Technologies AG
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*
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* This device driver implements the TPM interface as defined in the TCG PC
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* Client Platform TPM Profile (PTP) Specification for TPM 2.0 v1.04
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* Revision 14.
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*
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* It is based on the tpm_tis_spi device driver.
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*/
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#include <linux/i2c.h>
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#include <linux/crc-ccitt.h>
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#include "tpm_tis_core.h"
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/* TPM registers */
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#define TPM_I2C_LOC_SEL 0x00
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#define TPM_I2C_ACCESS 0x04
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#define TPM_I2C_INTERFACE_CAPABILITY 0x30
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#define TPM_I2C_DEVICE_ADDRESS 0x38
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#define TPM_I2C_DATA_CSUM_ENABLE 0x40
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#define TPM_DATA_CSUM 0x44
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#define TPM_I2C_DID_VID 0x48
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#define TPM_I2C_RID 0x4C
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/* TIS-compatible register address to avoid clash with TPM_ACCESS (0x00) */
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#define TPM_LOC_SEL 0x0FFF
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/* Mask to extract the I2C register from TIS register addresses */
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#define TPM_TIS_REGISTER_MASK 0x0FFF
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/* Default Guard Time of 250µs until interface capability register is read */
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#define GUARD_TIME_DEFAULT_MIN 250
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#define GUARD_TIME_DEFAULT_MAX 300
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/* Guard Time of 250µs after I2C slave NACK */
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#define GUARD_TIME_ERR_MIN 250
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#define GUARD_TIME_ERR_MAX 300
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/* Guard Time bit masks; SR is repeated start, RW is read then write, etc. */
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#define TPM_GUARD_TIME_SR_MASK 0x40000000
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#define TPM_GUARD_TIME_RR_MASK 0x00100000
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#define TPM_GUARD_TIME_RW_MASK 0x00080000
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#define TPM_GUARD_TIME_WR_MASK 0x00040000
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#define TPM_GUARD_TIME_WW_MASK 0x00020000
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#define TPM_GUARD_TIME_MIN_MASK 0x0001FE00
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#define TPM_GUARD_TIME_MIN_SHIFT 9
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/* Masks with bits that must be read zero */
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#define TPM_ACCESS_READ_ZERO 0x48
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#define TPM_INT_ENABLE_ZERO 0x7FFFFF6
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#define TPM_STS_READ_ZERO 0x23
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#define TPM_INTF_CAPABILITY_ZERO 0x0FFFF000
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#define TPM_I2C_INTERFACE_CAPABILITY_ZERO 0x80000000
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struct tpm_tis_i2c_phy {
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struct tpm_tis_data priv;
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struct i2c_client *i2c_client;
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bool guard_time_read;
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bool guard_time_write;
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u16 guard_time_min;
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u16 guard_time_max;
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u8 *io_buf;
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};
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static inline struct tpm_tis_i2c_phy *
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to_tpm_tis_i2c_phy(struct tpm_tis_data *data)
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{
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return container_of(data, struct tpm_tis_i2c_phy, priv);
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}
|
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|
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/*
|
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* tpm_tis_core uses the register addresses as defined in Table 19 "Allocation
|
||||
* of Register Space for FIFO TPM Access" of the TCG PC Client PTP
|
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* Specification. In order for this code to work together with tpm_tis_core,
|
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* those addresses need to mapped to the registers defined for I2C TPMs in
|
||||
* Table 51 "I2C-TPM Register Overview".
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||||
*
|
||||
* For most addresses this can be done by simply stripping off the locality
|
||||
* information from the address. A few addresses need to be mapped explicitly,
|
||||
* since the corresponding I2C registers have been moved around. TPM_LOC_SEL is
|
||||
* only defined for I2C TPMs and is also mapped explicitly here to distinguish
|
||||
* it from TPM_ACCESS(0).
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||||
*
|
||||
* Locality information is ignored, since this driver assumes exclusive access
|
||||
* to the TPM and always uses locality 0.
|
||||
*/
|
||||
static u8 tpm_tis_i2c_address_to_register(u32 addr)
|
||||
{
|
||||
addr &= TPM_TIS_REGISTER_MASK;
|
||||
|
||||
switch (addr) {
|
||||
case TPM_ACCESS(0):
|
||||
return TPM_I2C_ACCESS;
|
||||
case TPM_LOC_SEL:
|
||||
return TPM_I2C_LOC_SEL;
|
||||
case TPM_DID_VID(0):
|
||||
return TPM_I2C_DID_VID;
|
||||
case TPM_RID(0):
|
||||
return TPM_I2C_RID;
|
||||
default:
|
||||
return addr;
|
||||
}
|
||||
}
|
||||
|
||||
static int tpm_tis_i2c_retry_transfer_until_ack(struct tpm_tis_data *data,
|
||||
struct i2c_msg *msg)
|
||||
{
|
||||
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
|
||||
bool guard_time;
|
||||
int i = 0;
|
||||
int ret;
|
||||
|
||||
if (msg->flags & I2C_M_RD)
|
||||
guard_time = phy->guard_time_read;
|
||||
else
|
||||
guard_time = phy->guard_time_write;
|
||||
|
||||
do {
|
||||
ret = i2c_transfer(phy->i2c_client->adapter, msg, 1);
|
||||
if (ret < 0)
|
||||
usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
|
||||
else if (guard_time)
|
||||
usleep_range(phy->guard_time_min, phy->guard_time_max);
|
||||
/* retry on TPM NACK */
|
||||
} while (ret < 0 && i++ < TPM_RETRY);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Check that bits which must be read zero are not set */
|
||||
static int tpm_tis_i2c_sanity_check_read(u8 reg, u16 len, u8 *buf)
|
||||
{
|
||||
u32 zero_mask;
|
||||
u32 value;
|
||||
|
||||
switch (len) {
|
||||
case sizeof(u8):
|
||||
value = buf[0];
|
||||
break;
|
||||
case sizeof(u16):
|
||||
value = le16_to_cpup((__le16 *)buf);
|
||||
break;
|
||||
case sizeof(u32):
|
||||
value = le32_to_cpup((__le32 *)buf);
|
||||
break;
|
||||
default:
|
||||
/* unknown length, skip check */
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (reg) {
|
||||
case TPM_I2C_ACCESS:
|
||||
zero_mask = TPM_ACCESS_READ_ZERO;
|
||||
break;
|
||||
case TPM_INT_ENABLE(0) & TPM_TIS_REGISTER_MASK:
|
||||
zero_mask = TPM_INT_ENABLE_ZERO;
|
||||
break;
|
||||
case TPM_STS(0) & TPM_TIS_REGISTER_MASK:
|
||||
zero_mask = TPM_STS_READ_ZERO;
|
||||
break;
|
||||
case TPM_INTF_CAPS(0) & TPM_TIS_REGISTER_MASK:
|
||||
zero_mask = TPM_INTF_CAPABILITY_ZERO;
|
||||
break;
|
||||
case TPM_I2C_INTERFACE_CAPABILITY:
|
||||
zero_mask = TPM_I2C_INTERFACE_CAPABILITY_ZERO;
|
||||
break;
|
||||
default:
|
||||
/* unknown register, skip check */
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (unlikely((value & zero_mask) != 0x00)) {
|
||||
pr_debug("TPM I2C read of register 0x%02x failed sanity check: 0x%x\n", reg, value);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tpm_tis_i2c_read_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
|
||||
u8 *result, enum tpm_tis_io_mode io_mode)
|
||||
{
|
||||
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
|
||||
struct i2c_msg msg = { .addr = phy->i2c_client->addr };
|
||||
u8 reg = tpm_tis_i2c_address_to_register(addr);
|
||||
int i;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < TPM_RETRY; i++) {
|
||||
/* write register */
|
||||
msg.len = sizeof(reg);
|
||||
msg.buf = ®
|
||||
msg.flags = 0;
|
||||
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* read data */
|
||||
msg.buf = result;
|
||||
msg.len = len;
|
||||
msg.flags = I2C_M_RD;
|
||||
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = tpm_tis_i2c_sanity_check_read(reg, len, result);
|
||||
if (ret == 0)
|
||||
return 0;
|
||||
|
||||
usleep_range(GUARD_TIME_ERR_MIN, GUARD_TIME_ERR_MAX);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int tpm_tis_i2c_write_bytes(struct tpm_tis_data *data, u32 addr, u16 len,
|
||||
const u8 *value,
|
||||
enum tpm_tis_io_mode io_mode)
|
||||
{
|
||||
struct tpm_tis_i2c_phy *phy = to_tpm_tis_i2c_phy(data);
|
||||
struct i2c_msg msg = { .addr = phy->i2c_client->addr };
|
||||
u8 reg = tpm_tis_i2c_address_to_register(addr);
|
||||
int ret;
|
||||
|
||||
if (len > TPM_BUFSIZE - 1)
|
||||
return -EIO;
|
||||
|
||||
/* write register and data in one go */
|
||||
phy->io_buf[0] = reg;
|
||||
memcpy(phy->io_buf + sizeof(reg), value, len);
|
||||
|
||||
msg.len = sizeof(reg) + len;
|
||||
msg.buf = phy->io_buf;
|
||||
ret = tpm_tis_i2c_retry_transfer_until_ack(data, &msg);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tpm_tis_i2c_verify_crc(struct tpm_tis_data *data, size_t len,
|
||||
const u8 *value)
|
||||
{
|
||||
u16 crc_tpm, crc_host;
|
||||
int rc;
|
||||
|
||||
rc = tpm_tis_read16(data, TPM_DATA_CSUM, &crc_tpm);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
|
||||
/* reflect crc result, regardless of host endianness */
|
||||
crc_host = swab16(crc_ccitt(0, value, len));
|
||||
if (crc_tpm != crc_host)
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Guard Time:
|
||||
* After each I2C operation, the TPM might require the master to wait.
|
||||
* The time period is vendor-specific and must be read from the
|
||||
* TPM_I2C_INTERFACE_CAPABILITY register.
|
||||
*
|
||||
* Before the Guard Time is read (or after the TPM failed to send an I2C NACK),
|
||||
* a Guard Time of 250µs applies.
|
||||
*
|
||||
* Various flags in the same register indicate if a guard time is needed:
|
||||
* - SR: <I2C read with repeated start> <guard time> <I2C read>
|
||||
* - RR: <I2C read> <guard time> <I2C read>
|
||||
* - RW: <I2C read> <guard time> <I2C write>
|
||||
* - WR: <I2C write> <guard time> <I2C read>
|
||||
* - WW: <I2C write> <guard time> <I2C write>
|
||||
*
|
||||
* See TCG PC Client PTP Specification v1.04, 8.1.10 GUARD_TIME
|
||||
*/
|
||||
static int tpm_tis_i2c_init_guard_time(struct tpm_tis_i2c_phy *phy)
|
||||
{
|
||||
u32 i2c_caps;
|
||||
int ret;
|
||||
|
||||
phy->guard_time_read = true;
|
||||
phy->guard_time_write = true;
|
||||
phy->guard_time_min = GUARD_TIME_DEFAULT_MIN;
|
||||
phy->guard_time_max = GUARD_TIME_DEFAULT_MAX;
|
||||
|
||||
ret = tpm_tis_i2c_read_bytes(&phy->priv, TPM_I2C_INTERFACE_CAPABILITY,
|
||||
sizeof(i2c_caps), (u8 *)&i2c_caps,
|
||||
TPM_TIS_PHYS_32);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
phy->guard_time_read = (i2c_caps & TPM_GUARD_TIME_RR_MASK) ||
|
||||
(i2c_caps & TPM_GUARD_TIME_RW_MASK);
|
||||
phy->guard_time_write = (i2c_caps & TPM_GUARD_TIME_WR_MASK) ||
|
||||
(i2c_caps & TPM_GUARD_TIME_WW_MASK);
|
||||
phy->guard_time_min = (i2c_caps & TPM_GUARD_TIME_MIN_MASK) >>
|
||||
TPM_GUARD_TIME_MIN_SHIFT;
|
||||
/* guard_time_max = guard_time_min * 1.2 */
|
||||
phy->guard_time_max = phy->guard_time_min + phy->guard_time_min / 5;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
|
||||
|
||||
static const struct tpm_tis_phy_ops tpm_i2c_phy_ops = {
|
||||
.read_bytes = tpm_tis_i2c_read_bytes,
|
||||
.write_bytes = tpm_tis_i2c_write_bytes,
|
||||
.verify_crc = tpm_tis_i2c_verify_crc,
|
||||
};
|
||||
|
||||
static int tpm_tis_i2c_probe(struct i2c_client *dev,
|
||||
const struct i2c_device_id *id)
|
||||
{
|
||||
struct tpm_tis_i2c_phy *phy;
|
||||
const u8 crc_enable = 1;
|
||||
const u8 locality = 0;
|
||||
int ret;
|
||||
|
||||
phy = devm_kzalloc(&dev->dev, sizeof(struct tpm_tis_i2c_phy),
|
||||
GFP_KERNEL);
|
||||
if (!phy)
|
||||
return -ENOMEM;
|
||||
|
||||
phy->io_buf = devm_kzalloc(&dev->dev, TPM_BUFSIZE, GFP_KERNEL);
|
||||
if (!phy->io_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
phy->i2c_client = dev;
|
||||
|
||||
/* must precede all communication with the tpm */
|
||||
ret = tpm_tis_i2c_init_guard_time(phy);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_LOC_SEL, sizeof(locality),
|
||||
&locality, TPM_TIS_PHYS_8);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = tpm_tis_i2c_write_bytes(&phy->priv, TPM_I2C_DATA_CSUM_ENABLE,
|
||||
sizeof(crc_enable), &crc_enable,
|
||||
TPM_TIS_PHYS_8);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return tpm_tis_core_init(&dev->dev, &phy->priv, -1, &tpm_i2c_phy_ops,
|
||||
NULL);
|
||||
}
|
||||
|
||||
static int tpm_tis_i2c_remove(struct i2c_client *client)
|
||||
{
|
||||
struct tpm_chip *chip = i2c_get_clientdata(client);
|
||||
|
||||
tpm_chip_unregister(chip);
|
||||
tpm_tis_remove(chip);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id tpm_tis_i2c_id[] = {
|
||||
{ "tpm_tis_i2c", 0 },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(i2c, tpm_tis_i2c_id);
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id of_tis_i2c_match[] = {
|
||||
{ .compatible = "infineon,slb9673", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_tis_i2c_match);
|
||||
#endif
|
||||
|
||||
static struct i2c_driver tpm_tis_i2c_driver = {
|
||||
.driver = {
|
||||
.name = "tpm_tis_i2c",
|
||||
.pm = &tpm_tis_pm,
|
||||
.of_match_table = of_match_ptr(of_tis_i2c_match),
|
||||
},
|
||||
.probe = tpm_tis_i2c_probe,
|
||||
.remove = tpm_tis_i2c_remove,
|
||||
.id_table = tpm_tis_i2c_id,
|
||||
};
|
||||
module_i2c_driver(tpm_tis_i2c_driver);
|
||||
|
||||
MODULE_DESCRIPTION("TPM Driver for native I2C access");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -157,7 +157,7 @@ struct tcg_algorithm_info {
|
||||
* Return: size of the event on success, 0 on failure
|
||||
*/
|
||||
|
||||
static inline int __calc_tpm2_event_size(struct tcg_pcr_event2_head *event,
|
||||
static __always_inline int __calc_tpm2_event_size(struct tcg_pcr_event2_head *event,
|
||||
struct tcg_pcr_event *event_header,
|
||||
bool do_mapping)
|
||||
{
|
||||
|
||||
@ -114,7 +114,7 @@ static void drain_openssl_errors(void)
|
||||
bool __cond = (cond); \
|
||||
display_openssl_errors(__LINE__); \
|
||||
if (__cond) { \
|
||||
err(1, fmt, ## __VA_ARGS__); \
|
||||
errx(1, fmt, ## __VA_ARGS__); \
|
||||
} \
|
||||
} while(0)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user