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MIPS: math-emu: Define IEEE 754-2008 feature control bits

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Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.

For completeness define FIR.UFRP too.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Maciej W. Rozycki 2015-04-03 23:27:38 +01:00 committed by Ralf Baechle
parent c491cfa2ca
commit f1f3b7ebac
3 changed files with 17 additions and 9 deletions
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9
arch/mips/include/asm/mipsregs.h
View File

@ -708,6 +708,8 @@
#define MIPS_FPIR_W (_ULCAST_(1) << 20)
#define MIPS_FPIR_L (_ULCAST_(1) << 21)
#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
/*
@ -765,10 +767,13 @@
#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
/*
* Bits 18 - 20 of the FPU Status Register will be read as 0,
* Bits 22:20 of the FPU Status Register will be read as 0,
* and should be written as zero.
*/
#define FPU_CSR_RSVD 0x001c0000
#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
/*
* X the exception cause indicator

5
arch/mips/math-emu/cp1emu.c
View File

@ -919,8 +919,9 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
pr_debug("%p gpr[%d]->csr=%08x\n",
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
/* Don't write reserved bits. */
fcr31 = value & ~FPU_CSR_RSVD;
/* Don't write unsupported bits. */
fcr31 = value &
~(FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
break;
case FPCREG_FENR:

12
arch/mips/math-emu/ieee754.h
View File

@ -130,15 +130,17 @@ enum {
* The control status register
*/
struct _ieee754_csr {
__BITFIELD_FIELD(unsigned pad0:7,
__BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormalised numbers */
__BITFIELD_FIELD(unsigned c:1, /* condition */
__BITFIELD_FIELD(unsigned pad1:5,
__BITFIELD_FIELD(unsigned fcc:7, /* condition[7:1] */
__BITFIELD_FIELD(unsigned nod:1, /* set 1 for no denormals */
__BITFIELD_FIELD(unsigned c:1, /* condition[0] */
__BITFIELD_FIELD(unsigned pad0:3,
__BITFIELD_FIELD(unsigned abs2008:1, /* IEEE 754-2008 ABS/NEG.fmt */
__BITFIELD_FIELD(unsigned nan2008:1, /* IEEE 754-2008 NaN mode */
__BITFIELD_FIELD(unsigned cx:6, /* exceptions this operation */
__BITFIELD_FIELD(unsigned mx:5, /* exception enable mask */
__BITFIELD_FIELD(unsigned sx:5, /* exceptions total */
__BITFIELD_FIELD(unsigned rm:2, /* current rounding mode */
;))))))))
;))))))))))
};
#define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31))