mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-15 06:55:13 +08:00
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS update from Ralf Baechle:
"To avoid unnecessary risk and work the preemption fixes are combined
with some preparatory work that isn't strictly required. So it's
really just 3 fixes:
- Get is_compat_task() to do the right thing while simplifying it.
The unnecessary complexity hid a rarely striking bug which could be
triggered by ext3/ext4 under certain circumstances.
- Resolve a preemption issue in the irqflags.h functions for kernels
built to support pre-MIPS32 / pre-MIPS64 Release 2 processors.
- Fix the interrupt number of the MIPS Malta's CBUS UART."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Malta: Fix interupt number of CBUS UART.
MIPS: Make irqflags.h functions preempt-safe for non-mipsr2 cpus
MIPS: Remove irqflags.h dependency from bitops.h
MIPS: bitops.h: Change use of 'unsigned short' to 'int'
MIPS: compat: Delete now unused TIF_32BIT.
MIPS: compat: Implement is_compat_task() by testing for 32-bit address space.
MIPS: compat: Fix use of TIF_32BIT_ADDR vs _TIF_32BIT_ADDR
This commit is contained in:
Linus Torvalds
commit
f0c391131a
@ -30,6 +30,7 @@
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* measurement, and debugging facilities.
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*/
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#include <linux/irqflags.h>
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-l2c.h>
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#include <asm/octeon/cvmx-spinlock.h>
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@ -14,7 +14,6 @@
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#endif
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#include <linux/compiler.h>
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#include <linux/irqflags.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/byteorder.h> /* sigh ... */
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@ -44,6 +43,24 @@
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#define smp_mb__before_clear_bit() smp_mb__before_llsc()
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#define smp_mb__after_clear_bit() smp_llsc_mb()
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/*
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* These are the "slower" versions of the functions and are in bitops.c.
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* These functions call raw_local_irq_{save,restore}().
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*/
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void __mips_set_bit(unsigned long nr, volatile unsigned long *addr);
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void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr);
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void __mips_change_bit(unsigned long nr, volatile unsigned long *addr);
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int __mips_test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr);
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int __mips_test_and_set_bit_lock(unsigned long nr,
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volatile unsigned long *addr);
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int __mips_test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr);
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int __mips_test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr);
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/*
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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@ -57,7 +74,7 @@
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static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long temp;
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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@ -92,17 +109,8 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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: "=&r" (temp), "+m" (*m)
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: "ir" (1UL << bit));
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} while (unlikely(!temp));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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*a |= mask;
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raw_local_irq_restore(flags);
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}
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} else
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__mips_set_bit(nr, addr);
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}
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/*
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@ -118,7 +126,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
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static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long temp;
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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@ -153,17 +161,8 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
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: "=&r" (temp), "+m" (*m)
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: "ir" (~(1UL << bit)));
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} while (unlikely(!temp));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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*a &= ~mask;
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raw_local_irq_restore(flags);
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}
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} else
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__mips_clear_bit(nr, addr);
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}
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/*
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@ -191,7 +190,7 @@ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *ad
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*/
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static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
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@ -220,17 +219,8 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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: "=&r" (temp), "+m" (*m)
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: "ir" (1UL << bit));
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} while (unlikely(!temp));
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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*a ^= mask;
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raw_local_irq_restore(flags);
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}
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} else
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__mips_change_bit(nr, addr);
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}
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/*
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@ -244,7 +234,7 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
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static inline int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_mb__before_llsc();
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@ -281,18 +271,8 @@ static inline int test_and_set_bit(unsigned long nr,
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} while (unlikely(!res));
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res = temp & (1UL << bit);
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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res = (mask & *a);
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*a |= mask;
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raw_local_irq_restore(flags);
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}
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} else
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res = __mips_test_and_set_bit(nr, addr);
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smp_llsc_mb();
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@ -310,7 +290,7 @@ static inline int test_and_set_bit(unsigned long nr,
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static inline int test_and_set_bit_lock(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long res;
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if (kernel_uses_llsc && R10000_LLSC_WAR) {
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@ -345,18 +325,8 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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} while (unlikely(!res));
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res = temp & (1UL << bit);
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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res = (mask & *a);
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*a |= mask;
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raw_local_irq_restore(flags);
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}
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} else
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res = __mips_test_and_set_bit_lock(nr, addr);
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smp_llsc_mb();
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@ -373,7 +343,7 @@ static inline int test_and_set_bit_lock(unsigned long nr,
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static inline int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_mb__before_llsc();
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@ -428,18 +398,8 @@ static inline int test_and_clear_bit(unsigned long nr,
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} while (unlikely(!res));
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res = temp & (1UL << bit);
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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res = (mask & *a);
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*a &= ~mask;
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raw_local_irq_restore(flags);
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}
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} else
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res = __mips_test_and_clear_bit(nr, addr);
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smp_llsc_mb();
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@ -457,7 +417,7 @@ static inline int test_and_clear_bit(unsigned long nr,
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static inline int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned short bit = nr & SZLONG_MASK;
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int bit = nr & SZLONG_MASK;
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unsigned long res;
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smp_mb__before_llsc();
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@ -494,18 +454,8 @@ static inline int test_and_change_bit(unsigned long nr,
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} while (unlikely(!res));
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res = temp & (1UL << bit);
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} else {
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volatile unsigned long *a = addr;
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unsigned long mask;
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unsigned long flags;
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a += nr >> SZLONG_LOG;
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mask = 1UL << bit;
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raw_local_irq_save(flags);
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res = (mask & *a);
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*a ^= mask;
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raw_local_irq_restore(flags);
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}
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} else
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res = __mips_test_and_change_bit(nr, addr);
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smp_llsc_mb();
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@ -290,7 +290,7 @@ struct compat_shmid64_ds {
|
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static inline int is_compat_task(void)
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{
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return test_thread_flag(TIF_32BIT);
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return test_thread_flag(TIF_32BIT_ADDR);
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}
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#endif /* _ASM_COMPAT_H */
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@ -15,6 +15,7 @@
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#include <linux/compiler.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
|
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#include <linux/irqflags.h>
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#include <asm/addrspace.h>
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#include <asm/bug.h>
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@ -16,6 +16,105 @@
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#include <linux/compiler.h>
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#include <asm/hazards.h>
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#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC)
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__asm__(
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" .macro arch_local_irq_disable\n"
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" .set push \n"
|
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" .set noat \n"
|
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" di \n"
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" irq_disable_hazard \n"
|
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" .set pop \n"
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" .endm \n");
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|
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static inline void arch_local_irq_disable(void)
|
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{
|
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__asm__ __volatile__(
|
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"arch_local_irq_disable"
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: /* no outputs */
|
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: /* no inputs */
|
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: "memory");
|
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}
|
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|
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|
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__asm__(
|
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" .macro arch_local_irq_save result \n"
|
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" .set push \n"
|
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" .set reorder \n"
|
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" .set noat \n"
|
||||
" di \\result \n"
|
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" andi \\result, 1 \n"
|
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" irq_disable_hazard \n"
|
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" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
static inline unsigned long arch_local_irq_save(void)
|
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{
|
||||
unsigned long flags;
|
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asm volatile("arch_local_irq_save\t%0"
|
||||
: "=r" (flags)
|
||||
: /* no inputs */
|
||||
: "memory");
|
||||
return flags;
|
||||
}
|
||||
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_restore flags \n"
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
#if defined(CONFIG_IRQ_CPU)
|
||||
/*
|
||||
* Slow, but doesn't suffer from a relatively unlikely race
|
||||
* condition we're having since days 1.
|
||||
*/
|
||||
" beqz \\flags, 1f \n"
|
||||
" di \n"
|
||||
" ei \n"
|
||||
"1: \n"
|
||||
#else
|
||||
/*
|
||||
* Fast, dangerous. Life is fun, life is good.
|
||||
*/
|
||||
" mfc0 $1, $12 \n"
|
||||
" ins $1, \\flags, 0, 1 \n"
|
||||
" mtc0 $1, $12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
static inline void arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static inline void __arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
}
|
||||
#else
|
||||
/* Functions that require preempt_{dis,en}able() are in mips-atomic.c */
|
||||
void arch_local_irq_disable(void);
|
||||
unsigned long arch_local_irq_save(void);
|
||||
void arch_local_irq_restore(unsigned long flags);
|
||||
void __arch_local_irq_restore(unsigned long flags);
|
||||
#endif /* if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_MIPS_MT_SMTC) */
|
||||
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_enable \n"
|
||||
" .set push \n"
|
||||
@ -57,55 +156,6 @@ static inline void arch_local_irq_enable(void)
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* For cli() we have to insert nops to make sure that the new value
|
||||
* has actually arrived in the status register before the end of this
|
||||
* macro.
|
||||
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
|
||||
* no nops at all.
|
||||
*/
|
||||
/*
|
||||
* For TX49, operating only IE bit is not enough.
|
||||
*
|
||||
* If mfc0 $12 follows store and the mfc0 is last instruction of a
|
||||
* page and fetching the next instruction causes TLB miss, the result
|
||||
* of the mfc0 might wrongly contain EXL bit.
|
||||
*
|
||||
* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
|
||||
*
|
||||
* Workaround: mask EXL bit of the result or place a nop before mfc0.
|
||||
*/
|
||||
__asm__(
|
||||
" .macro arch_local_irq_disable\n"
|
||||
" .set push \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
" mfc0 $1, $2, 1 \n"
|
||||
" ori $1, 0x400 \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $2, 1 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
" di \n"
|
||||
#else
|
||||
" mfc0 $1,$12 \n"
|
||||
" ori $1,0x1f \n"
|
||||
" xori $1,0x1f \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1,$12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
static inline void arch_local_irq_disable(void)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_disable"
|
||||
: /* no outputs */
|
||||
: /* no inputs */
|
||||
: "memory");
|
||||
}
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_save_flags flags \n"
|
||||
" .set push \n"
|
||||
@ -125,113 +175,6 @@ static inline unsigned long arch_local_save_flags(void)
|
||||
return flags;
|
||||
}
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_save result \n"
|
||||
" .set push \n"
|
||||
" .set reorder \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
" mfc0 \\result, $2, 1 \n"
|
||||
" ori $1, \\result, 0x400 \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $2, 1 \n"
|
||||
" andi \\result, \\result, 0x400 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
" di \\result \n"
|
||||
" andi \\result, 1 \n"
|
||||
#else
|
||||
" mfc0 \\result, $12 \n"
|
||||
" ori $1, \\result, 0x1f \n"
|
||||
" xori $1, 0x1f \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
static inline unsigned long arch_local_irq_save(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
asm volatile("arch_local_irq_save\t%0"
|
||||
: "=r" (flags)
|
||||
: /* no inputs */
|
||||
: "memory");
|
||||
return flags;
|
||||
}
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_restore flags \n"
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
"mfc0 $1, $2, 1 \n"
|
||||
"andi \\flags, 0x400 \n"
|
||||
"ori $1, 0x400 \n"
|
||||
"xori $1, 0x400 \n"
|
||||
"or \\flags, $1 \n"
|
||||
"mtc0 \\flags, $2, 1 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
|
||||
/*
|
||||
* Slow, but doesn't suffer from a relatively unlikely race
|
||||
* condition we're having since days 1.
|
||||
*/
|
||||
" beqz \\flags, 1f \n"
|
||||
" di \n"
|
||||
" ei \n"
|
||||
"1: \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
/*
|
||||
* Fast, dangerous. Life is fun, life is good.
|
||||
*/
|
||||
" mfc0 $1, $12 \n"
|
||||
" ins $1, \\flags, 0, 1 \n"
|
||||
" mtc0 $1, $12 \n"
|
||||
#else
|
||||
" mfc0 $1, $12 \n"
|
||||
" andi \\flags, 1 \n"
|
||||
" ori $1, 0x1f \n"
|
||||
" xori $1, 0x1f \n"
|
||||
" or \\flags, $1 \n"
|
||||
" mtc0 \\flags, $12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
|
||||
static inline void arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
/*
|
||||
* SMTC kernel needs to do a software replay of queued
|
||||
* IPIs, at the cost of branch and call overhead on each
|
||||
* local_irq_restore()
|
||||
*/
|
||||
if (unlikely(!(flags & 0x0400)))
|
||||
smtc_ipi_replay();
|
||||
#endif
|
||||
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static inline void __arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
{
|
||||
@ -245,7 +188,7 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif /* #ifndef __ASSEMBLY__ */
|
||||
|
||||
/*
|
||||
* Do the CPU's IRQ-state tracing from assembly code.
|
||||
|
||||
@ -112,12 +112,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
|
||||
#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
|
||||
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
|
||||
|
||||
#ifdef CONFIG_MIPS32_O32
|
||||
#define TIF_32BIT TIF_32BIT_REGS
|
||||
#elif defined(CONFIG_MIPS32_N32)
|
||||
#define TIF_32BIT _TIF_32BIT_ADDR
|
||||
#endif /* CONFIG_MIPS32_O32 */
|
||||
|
||||
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
|
||||
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
|
||||
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
|
||||
|
||||
@ -2,8 +2,9 @@
|
||||
# Makefile for MIPS-specific library files..
|
||||
#
|
||||
|
||||
lib-y += csum_partial.o delay.o memcpy.o memset.o \
|
||||
strlen_user.o strncpy_user.o strnlen_user.o uncached.o
|
||||
lib-y += bitops.o csum_partial.o delay.o memcpy.o memset.o \
|
||||
mips-atomic.o strlen_user.o strncpy_user.o \
|
||||
strnlen_user.o uncached.o
|
||||
|
||||
obj-y += iomap.o
|
||||
obj-$(CONFIG_PCI) += iomap-pci.o
|
||||
|
||||
179
arch/mips/lib/bitops.c
Normal file
179
arch/mips/lib/bitops.c
Normal file
@ -0,0 +1,179 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (c) 1994-1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org)
|
||||
* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
|
||||
*/
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
|
||||
/**
|
||||
* __mips_set_bit - Atomically set a bit in memory. This is called by
|
||||
* set_bit() if it cannot find a faster solution.
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*/
|
||||
void __mips_set_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
*a |= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_set_bit);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_clear_bit - Clears a bit in memory. This is called by clear_bit() if
|
||||
* it cannot find a faster solution.
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to start counting from
|
||||
*/
|
||||
void __mips_clear_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
*a &= ~mask;
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_clear_bit);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_change_bit - Toggle a bit in memory. This is called by change_bit()
|
||||
* if it cannot find a faster solution.
|
||||
* @nr: Bit to change
|
||||
* @addr: Address to start counting from
|
||||
*/
|
||||
void __mips_change_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
*a ^= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_change_bit);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_test_and_set_bit - Set a bit and return its old value. This is
|
||||
* called by test_and_set_bit() if it cannot find a faster solution.
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*/
|
||||
int __mips_test_and_set_bit(unsigned long nr,
|
||||
volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
*a |= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_test_and_set_bit);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_test_and_set_bit_lock - Set a bit and return its old value. This is
|
||||
* called by test_and_set_bit_lock() if it cannot find a faster solution.
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*/
|
||||
int __mips_test_and_set_bit_lock(unsigned long nr,
|
||||
volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
*a |= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_test_and_set_bit_lock);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_test_and_clear_bit - Clear a bit and return its old value. This is
|
||||
* called by test_and_clear_bit() if it cannot find a faster solution.
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to count from
|
||||
*/
|
||||
int __mips_test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
*a &= ~mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_test_and_clear_bit);
|
||||
|
||||
|
||||
/**
|
||||
* __mips_test_and_change_bit - Change a bit and return its old value. This is
|
||||
* called by test_and_change_bit() if it cannot find a faster solution.
|
||||
* @nr: Bit to change
|
||||
* @addr: Address to count from
|
||||
*/
|
||||
int __mips_test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
|
||||
{
|
||||
volatile unsigned long *a = addr;
|
||||
unsigned bit = nr & SZLONG_MASK;
|
||||
unsigned long mask;
|
||||
unsigned long flags;
|
||||
unsigned long res;
|
||||
|
||||
a += nr >> SZLONG_LOG;
|
||||
mask = 1UL << bit;
|
||||
raw_local_irq_save(flags);
|
||||
res = (mask & *a);
|
||||
*a ^= mask;
|
||||
raw_local_irq_restore(flags);
|
||||
return res;
|
||||
}
|
||||
EXPORT_SYMBOL(__mips_test_and_change_bit);
|
||||
176
arch/mips/lib/mips-atomic.c
Normal file
176
arch/mips/lib/mips-atomic.c
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
|
||||
* Copyright (C) 1996 by Paul M. Antoine
|
||||
* Copyright (C) 1999 Silicon Graphics
|
||||
* Copyright (C) 2000 MIPS Technologies, Inc.
|
||||
*/
|
||||
#include <asm/irqflags.h>
|
||||
#include <asm/hazards.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/preempt.h>
|
||||
#include <linux/export.h>
|
||||
|
||||
#if !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC)
|
||||
|
||||
/*
|
||||
* For cli() we have to insert nops to make sure that the new value
|
||||
* has actually arrived in the status register before the end of this
|
||||
* macro.
|
||||
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
|
||||
* no nops at all.
|
||||
*/
|
||||
/*
|
||||
* For TX49, operating only IE bit is not enough.
|
||||
*
|
||||
* If mfc0 $12 follows store and the mfc0 is last instruction of a
|
||||
* page and fetching the next instruction causes TLB miss, the result
|
||||
* of the mfc0 might wrongly contain EXL bit.
|
||||
*
|
||||
* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
|
||||
*
|
||||
* Workaround: mask EXL bit of the result or place a nop before mfc0.
|
||||
*/
|
||||
__asm__(
|
||||
" .macro arch_local_irq_disable\n"
|
||||
" .set push \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
" mfc0 $1, $2, 1 \n"
|
||||
" ori $1, 0x400 \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $2, 1 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
/* see irqflags.h for inline function */
|
||||
#else
|
||||
" mfc0 $1,$12 \n"
|
||||
" ori $1,0x1f \n"
|
||||
" xori $1,0x1f \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1,$12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
void arch_local_irq_disable(void)
|
||||
{
|
||||
preempt_disable();
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_disable"
|
||||
: /* no outputs */
|
||||
: /* no inputs */
|
||||
: "memory");
|
||||
preempt_enable();
|
||||
}
|
||||
EXPORT_SYMBOL(arch_local_irq_disable);
|
||||
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_save result \n"
|
||||
" .set push \n"
|
||||
" .set reorder \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
" mfc0 \\result, $2, 1 \n"
|
||||
" ori $1, \\result, 0x400 \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $2, 1 \n"
|
||||
" andi \\result, \\result, 0x400 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
/* see irqflags.h for inline function */
|
||||
#else
|
||||
" mfc0 \\result, $12 \n"
|
||||
" ori $1, \\result, 0x1f \n"
|
||||
" xori $1, 0x1f \n"
|
||||
" .set noreorder \n"
|
||||
" mtc0 $1, $12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
unsigned long arch_local_irq_save(void)
|
||||
{
|
||||
unsigned long flags;
|
||||
preempt_disable();
|
||||
asm volatile("arch_local_irq_save\t%0"
|
||||
: "=r" (flags)
|
||||
: /* no inputs */
|
||||
: "memory");
|
||||
preempt_enable();
|
||||
return flags;
|
||||
}
|
||||
EXPORT_SYMBOL(arch_local_irq_save);
|
||||
|
||||
|
||||
__asm__(
|
||||
" .macro arch_local_irq_restore flags \n"
|
||||
" .set push \n"
|
||||
" .set noreorder \n"
|
||||
" .set noat \n"
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
"mfc0 $1, $2, 1 \n"
|
||||
"andi \\flags, 0x400 \n"
|
||||
"ori $1, 0x400 \n"
|
||||
"xori $1, 0x400 \n"
|
||||
"or \\flags, $1 \n"
|
||||
"mtc0 \\flags, $2, 1 \n"
|
||||
#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
|
||||
/* see irqflags.h for inline function */
|
||||
#elif defined(CONFIG_CPU_MIPSR2)
|
||||
/* see irqflags.h for inline function */
|
||||
#else
|
||||
" mfc0 $1, $12 \n"
|
||||
" andi \\flags, 1 \n"
|
||||
" ori $1, 0x1f \n"
|
||||
" xori $1, 0x1f \n"
|
||||
" or \\flags, $1 \n"
|
||||
" mtc0 \\flags, $12 \n"
|
||||
#endif
|
||||
" irq_disable_hazard \n"
|
||||
" .set pop \n"
|
||||
" .endm \n");
|
||||
|
||||
void arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_SMTC
|
||||
/*
|
||||
* SMTC kernel needs to do a software replay of queued
|
||||
* IPIs, at the cost of branch and call overhead on each
|
||||
* local_irq_restore()
|
||||
*/
|
||||
if (unlikely(!(flags & 0x0400)))
|
||||
smtc_ipi_replay();
|
||||
#endif
|
||||
preempt_disable();
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
preempt_enable();
|
||||
}
|
||||
EXPORT_SYMBOL(arch_local_irq_restore);
|
||||
|
||||
|
||||
void __arch_local_irq_restore(unsigned long flags)
|
||||
{
|
||||
unsigned long __tmp1;
|
||||
|
||||
preempt_disable();
|
||||
__asm__ __volatile__(
|
||||
"arch_local_irq_restore\t%0"
|
||||
: "=r" (__tmp1)
|
||||
: "0" (flags)
|
||||
: "memory");
|
||||
preempt_enable();
|
||||
}
|
||||
EXPORT_SYMBOL(__arch_local_irq_restore);
|
||||
|
||||
#endif /* !defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_MIPS_MT_SMTC) */
|
||||
@ -29,6 +29,7 @@
|
||||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/mips-boards/maltaint.h>
|
||||
#include <mtd/mtd-abi.h>
|
||||
|
||||
#define SMC_PORT(base, int) \
|
||||
@ -48,7 +49,7 @@ static struct plat_serial8250_port uart8250_data[] = {
|
||||
SMC_PORT(0x2F8, 3),
|
||||
{
|
||||
.mapbase = 0x1f000900, /* The CBUS UART */
|
||||
.irq = MIPS_CPU_IRQ_BASE + 2,
|
||||
.irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
|
||||
.uartclk = 3686400, /* Twice the usual clk! */
|
||||
.iotype = UPIO_MEM32,
|
||||
.flags = CBUS_UART_FLAGS,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user