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powerpc/64s/exception: move EXCEPTION_PROLOG_2* to a more logical place
No generated code change. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
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@ -174,62 +174,6 @@
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ori reg,reg,(ABS_ADDR(label))@l; \
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addis reg,reg,(ABS_ADDR(label))@h
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.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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.endif
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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.if \hsrr
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mtspr SPRN_HSRR0,r12
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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HRFI_TO_KERNEL
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.else
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mtspr SPRN_SRR0,r12
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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RFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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.endm
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.macro EXCEPTION_PROLOG_2_VIRT label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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mtctr r12
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.if \hsrr
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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bctr
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#else
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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b \label
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#endif
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.endm
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/* Exception register prefixes */
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#define EXC_HV 1
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#define EXC_STD 0
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@ -340,6 +284,63 @@ END_FTR_SECTION_NESTED(ftr,ftr,943)
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std r10,\area\()+EX_R13(r13)
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.endm
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.macro EXCEPTION_PROLOG_2_REAL label, hsrr, set_ri
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ld r10,PACAKMSR(r13) /* get MSR value for kernel */
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.if ! \set_ri
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xori r10,r10,MSR_RI /* Clear MSR_RI */
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.endif
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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.if \hsrr
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mtspr SPRN_HSRR0,r12
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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mtspr SPRN_HSRR1,r10
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HRFI_TO_KERNEL
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.else
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mtspr SPRN_SRR0,r12
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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mtspr SPRN_SRR1,r10
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RFI_TO_KERNEL
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.endif
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b . /* prevent speculative execution */
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.endm
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.macro EXCEPTION_PROLOG_2_VIRT label, hsrr
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#ifdef CONFIG_RELOCATABLE
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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.endif
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LOAD_HANDLER(r12, \label\())
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mtctr r12
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.if \hsrr
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r12,SPRN_SRR1 /* and HSRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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bctr
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#else
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.if \hsrr
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mfspr r11,SPRN_HSRR0 /* save HSRR0 */
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mfspr r12,SPRN_HSRR1 /* and HSRR1 */
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.else
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mfspr r11,SPRN_SRR0 /* save SRR0 */
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mfspr r12,SPRN_SRR1 /* and SRR1 */
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.endif
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li r10,MSR_RI
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mtmsrd r10,1 /* Set RI (EE=0) */
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b \label
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#endif
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.endm
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* If hv is possible, interrupts come into to the hv version
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