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ath5k: Update PCU code
* In set_opmode don't handle antenna settings and preserve other STA_ID1 settings (shouldn't matter because we call it during reset but it makes things cleaner) Also set properly AP/ADHOC indicator flag on CFG while setting AP/ADHOC modes and always enable key search mode. * Properly set BSSID Mask during reset (cache it and reuse it durring set_associd) * Update beacon_init to flush pending BMISS interrupts and handle setting of adhoc beacon ATIM policy flag for ad-hoc mode. Also set TSF to 0 to start TSF increment on AP mode. We need to handle sleep timers for AR5212 there + add support for PCF. * Properly clean MIC key from keytable when TKIP is used (Bob is working on set_key function etc so i leave it for now). Tested on AR5212 (Hainan) and AR5413 and works fine v2 Set PISR on AR5211+ and ISR on AR5210, got to sleep more ;-) Changes-Licensed-under: ISC Signed-Off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
John W. Linville
parent
2c706002fc
commit
f07a6c495e
@ -1093,10 +1093,11 @@ struct ath5k_hw {
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u8 ah_sta_id[ETH_ALEN];
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/* Current BSSID we are trying to assoc to / creating.
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/* Current BSSID we are trying to assoc to / create.
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* This is passed by mac80211 on config_interface() and cached here for
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* use in resets */
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u8 ah_bssid[ETH_ALEN];
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u8 ah_bssid_mask[ETH_ALEN];
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u32 ah_gpio[AR5K_MAX_GPIO];
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int ah_gpio_npins;
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@ -46,34 +46,45 @@ int ath5k_hw_set_opmode(struct ath5k_hw *ah)
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{
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u32 pcu_reg, beacon_reg, low_id, high_id;
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pcu_reg = 0;
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/* Preserve rest settings */
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pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
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pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
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| AR5K_STA_ID1_KEYSRCH_MODE
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| (ah->ah_version == AR5K_AR5210 ?
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(AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
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beacon_reg = 0;
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ATH5K_TRACE(ah->ah_sc);
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switch (ah->ah_op_mode) {
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case NL80211_IFTYPE_ADHOC:
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pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
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(ah->ah_version == AR5K_AR5210 ?
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AR5K_STA_ID1_NO_PSPOLL : 0);
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pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
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beacon_reg |= AR5K_BCR_ADHOC;
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if (ah->ah_version == AR5K_AR5210)
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pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
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else
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AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
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break;
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case NL80211_IFTYPE_AP:
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case NL80211_IFTYPE_MESH_POINT:
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pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
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(ah->ah_version == AR5K_AR5210 ?
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AR5K_STA_ID1_NO_PSPOLL : 0);
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pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
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beacon_reg |= AR5K_BCR_AP;
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if (ah->ah_version == AR5K_AR5210)
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pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
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else
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AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_ADHOC);
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break;
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case NL80211_IFTYPE_STATION:
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pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
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(ah->ah_version == AR5K_AR5210 ?
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pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
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| (ah->ah_version == AR5K_AR5210 ?
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AR5K_STA_ID1_PWR_SV : 0);
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case NL80211_IFTYPE_MONITOR:
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pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
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(ah->ah_version == AR5K_AR5210 ?
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pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
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| (ah->ah_version == AR5K_AR5210 ?
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AR5K_STA_ID1_NO_PSPOLL : 0);
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break;
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@ -130,6 +141,8 @@ void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
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ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
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}
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/* TODO: Handle ANI stats */
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}
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/**
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@ -254,6 +267,10 @@ void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
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* @mac: The card's mac address
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*
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* Set station id on hw using the provided mac address
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*
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* NOTE: This is only called during attach, don't call it
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* on reset because it overwrites all AR5K_STA_ID1 settings.
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* We have set_opmode (above) for reset.
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*/
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int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
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{
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@ -290,8 +307,10 @@ void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
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* Set simple BSSID mask on 5212
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*/
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if (ah->ah_version == AR5K_AR5212) {
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ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
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ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
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ath5k_hw_reg_write(ah, AR5K_LOW_ID(ah->ah_bssid_mask),
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AR5K_BSS_IDM0);
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ath5k_hw_reg_write(ah, AR5K_HIGH_ID(ah->ah_bssid_mask),
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AR5K_BSS_IDM1);
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}
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/*
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@ -415,6 +434,9 @@ int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
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u32 low_id, high_id;
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ATH5K_TRACE(ah->ah_sc);
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/* Cache bssid mask so that we can restore it
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* on reset */
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memcpy(ah->ah_bssid_mask, mask, ETH_ALEN);
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if (ah->ah_version == AR5K_AR5212) {
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low_id = AR5K_LOW_ID(mask);
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high_id = AR5K_HIGH_ID(mask);
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@ -576,7 +598,7 @@ void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
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filter |= AR5K_RX_FILTER_PROM;
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}
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/*Zero length DMA*/
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/*Zero length DMA (phy error reporting) */
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if (data)
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AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
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else
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@ -661,7 +683,12 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
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* Set the additional timers by mode
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*/
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switch (ah->ah_op_mode) {
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case NL80211_IFTYPE_MONITOR:
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case NL80211_IFTYPE_STATION:
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/* In STA mode timer1 is used as next wakeup
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* timer and timer2 as next CFP duration start
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* timer. Both in 1/8TUs. */
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/* TODO: PCF handling */
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if (ah->ah_version == AR5K_AR5210) {
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timer1 = 0xffffffff;
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timer2 = 0xffffffff;
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@ -669,27 +696,60 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
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timer1 = 0x0000ffff;
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timer2 = 0x0007ffff;
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}
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/* Mark associated AP as PCF incapable for now */
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AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
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break;
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case NL80211_IFTYPE_ADHOC:
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AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
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default:
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/* On non-STA modes timer1 is used as next DMA
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* beacon alert (DBA) timer and timer2 as next
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* software beacon alert. Both in 1/8TUs. */
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timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
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timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
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break;
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}
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/* Timer3 marks the end of our ATIM window
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* a zero length window is not allowed because
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* we 'll get no beacons */
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timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
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/*
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* Set the beacon register and enable all timers.
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* (next beacon, DMA beacon, software beacon, ATIM window time)
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*/
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ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
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/* When in AP mode zero timer0 to start TSF */
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if (ah->ah_op_mode == NL80211_IFTYPE_AP)
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ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
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else
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ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
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ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
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ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
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ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
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/* Force a TSF reset if requested and enable beacons */
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if (interval & AR5K_BEACON_RESET_TSF)
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ath5k_hw_reset_tsf(ah);
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ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
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AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
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AR5K_BEACON);
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AR5K_BEACON_ENABLE),
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AR5K_BEACON);
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/* Flush any pending BMISS interrupts on ISR by
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* performing a clear-on-write operation on PISR
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* register for the BMISS bit (writing a bit on
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* ISR togles a reset for that bit and leaves
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* the rest bits intact) */
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if (ah->ah_version == AR5K_AR5210)
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ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
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else
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ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
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/* TODO: Set enchanced sleep registers on AR5212
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* based on vif->bss_conf params, until then
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* disable power save reporting.*/
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AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
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}
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#if 0
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@ -899,14 +959,25 @@ int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
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*/
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int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
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{
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unsigned int i;
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unsigned int i, type;
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ATH5K_TRACE(ah->ah_sc);
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AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
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type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
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for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
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ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
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/* Reset associated MIC entry if TKIP
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* is enabled located at offset (entry + 64) */
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if (type == AR5K_KEYTABLE_TYPE_TKIP) {
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entry = entry + AR5K_KEYTABLE_MIC_OFFSET;
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AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
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for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
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ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
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}
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/*
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* Set NULL encryption on AR5212+
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*
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@ -1114,14 +1114,16 @@
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#define AR5K_PCU_MAX 0x8fff
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/*
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* First station id register (MAC address in lower 32 bits)
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* First station id register (Lower 32 bits of MAC address)
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*/
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#define AR5K_STA_ID0 0x8000
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#define AR5K_STA_ID0 0x8000
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#define AR5K_STA_ID0_ARRD_L32 0xffffffff
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/*
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* Second station id register (MAC address in upper 16 bits)
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* Second station id register (Upper 16 bits of MAC address + PCU settings)
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*/
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#define AR5K_STA_ID1 0x8004 /* Register Address */
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#define AR5K_STA_ID1_ADDR_U16 0x0000ffff /* Upper 16 bits of MAC addres */
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#define AR5K_STA_ID1_AP 0x00010000 /* Set AP mode */
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#define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
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#define AR5K_STA_ID1_PWR_SV 0x00040000 /* Power save reporting */
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@ -1811,6 +1813,10 @@
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#define AR5K_KEYTABLE_MAC1(_n) AR5K_KEYTABLE_OFF(_n, 7)
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#define AR5K_KEYTABLE_VALID 0x00008000
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/* If key type is TKIP and MIC is enabled
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* MIC key goes in offset entry + 64 */
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#define AR5K_KEYTABLE_MIC_OFFSET 64
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/* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit
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* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit
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* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit
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