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drm/amdgpu: Added ASIC specific checks in gfxhub V1.1 get XGMI info
Added max hive/node info checks per supported ASIC Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -33,16 +33,31 @@ int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
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u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
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u32 max_region =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
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u32 max_num_physical_nodes = 0;
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u32 max_physical_node_id = 0;
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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max_num_physical_nodes = 4;
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max_physical_node_id = 3;
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break;
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case CHIP_ARCTURUS:
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max_num_physical_nodes = 8;
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max_physical_node_id = 7;
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break;
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default:
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return -EINVAL;
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}
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/* PF_MAX_REGION=0 means xgmi is disabled */
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if (max_region) {
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adev->gmc.xgmi.num_physical_nodes = max_region + 1;
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if (adev->gmc.xgmi.num_physical_nodes > 4)
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if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
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return -EINVAL;
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adev->gmc.xgmi.physical_node_id =
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REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
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if (adev->gmc.xgmi.physical_node_id > 3)
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if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
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return -EINVAL;
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adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
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RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
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