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Intel-IOMMU, intr-remap: source-id checking
To support domain-isolation usages, the platform hardware must be capable of uniquely identifying the requestor (source-id) for each interrupt message. Without source-id checking for interrupt remapping , a rouge guest/VM with assigned devices can launch interrupt attacks to bring down anothe guest/VM or the VMM itself. This patch adds source-id checking for interrupt remapping, and then really isolates interrupts for guests/VMs with assigned devices. Because PCI subsystem is not initialized yet when set up IOAPIC entries, use read_pci_config_byte to access PCI config space directly. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -1414,6 +1414,9 @@ int setup_ioapic_entry(int apic_id, int irq,
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irte.vector = vector;
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irte.dest_id = IRTE_DEST(destination);
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/* Set source-id of interrupt request */
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set_ioapic_sid(&irte, apic_id);
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modify_irte(irq, &irte);
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ir_entry->index2 = (index >> 15) & 0x1;
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@ -3290,6 +3293,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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/* Set source-id of interrupt request */
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set_msi_sid(&irte, pdev);
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modify_irte(irq, &irte);
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msg->address_hi = MSI_ADDR_BASE_HI;
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@ -10,6 +10,8 @@
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#include <linux/intel-iommu.h>
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#include "intr_remapping.h"
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#include <acpi/acpi.h>
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#include <asm/pci-direct.h>
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#include "pci.h"
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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@ -418,6 +420,91 @@ int free_irte(int irq)
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return rc;
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}
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/*
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* source validation type
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*/
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#define SVT_NO_VERIFY 0x0 /* no verification is required */
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#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fiels */
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#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
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/*
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* source-id qualifier
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*/
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#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
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#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
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* the third least significant bit
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*/
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#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
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* the second and third least significant bits
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*/
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#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
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* the least three significant bits
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*/
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/*
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* set SVT, SQ and SID fields of irte to verify
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* source ids of interrupt requests
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*/
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static void set_irte_sid(struct irte *irte, unsigned int svt,
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unsigned int sq, unsigned int sid)
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{
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irte->svt = svt;
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irte->sq = sq;
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irte->sid = sid;
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}
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int set_ioapic_sid(struct irte *irte, int apic)
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{
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int i;
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u16 sid = 0;
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if (!irte)
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return -1;
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for (i = 0; i < MAX_IO_APICS; i++) {
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if (ir_ioapic[i].id == apic) {
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sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
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break;
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}
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}
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if (sid == 0) {
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pr_warning("Failed to set source-id of IOAPIC (%d)\n", apic);
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return -1;
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}
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set_irte_sid(irte, 1, 0, sid);
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return 0;
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}
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int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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{
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struct pci_dev *bridge;
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if (!irte || !dev)
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return -1;
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/* PCIe device or Root Complex integrated PCI device */
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if (dev->is_pcie || !dev->bus->parent) {
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
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(dev->bus->number << 8) | dev->devfn);
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return 0;
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}
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bridge = pci_find_upstream_pcie_bridge(dev);
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if (bridge) {
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if (bridge->is_pcie) /* this is a PCIE-to-PCI/PCIX bridge */
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set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
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(bridge->bus->number << 8) | dev->bus->number);
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else /* this is a legacy PCI bridge */
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set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
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(bridge->bus->number << 8) | bridge->devfn);
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}
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return 0;
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}
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static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
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{
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u64 addr;
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@ -624,6 +711,35 @@ error:
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return -1;
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}
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static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
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struct intel_iommu *iommu)
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{
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struct acpi_dmar_pci_path *path;
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u8 bus;
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int count;
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bus = scope->bus;
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path = (struct acpi_dmar_pci_path *)(scope + 1);
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count = (scope->length - sizeof(struct acpi_dmar_device_scope))
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/ sizeof(struct acpi_dmar_pci_path);
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while (--count > 0) {
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/*
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* Access PCI directly due to the PCI
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* subsystem isn't initialized yet.
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*/
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bus = read_pci_config_byte(bus, path->dev, path->fn,
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PCI_SECONDARY_BUS);
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path++;
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}
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ir_ioapic[ir_ioapic_num].bus = bus;
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ir_ioapic[ir_ioapic_num].devfn = PCI_DEVFN(path->dev, path->fn);
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ir_ioapic[ir_ioapic_num].iommu = iommu;
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ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
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ir_ioapic_num++;
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}
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static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
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struct intel_iommu *iommu)
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{
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@ -648,9 +764,7 @@ static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
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" 0x%Lx\n", scope->enumeration_id,
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drhd->address);
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ir_ioapic[ir_ioapic_num].iommu = iommu;
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ir_ioapic[ir_ioapic_num].id = scope->enumeration_id;
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ir_ioapic_num++;
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ir_parse_one_ioapic_scope(scope, iommu);
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}
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start += scope->length;
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}
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@ -3,6 +3,8 @@
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struct ioapic_scope {
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struct intel_iommu *iommu;
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unsigned int id;
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unsigned int bus; /* PCI bus number */
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unsigned int devfn; /* PCI devfn number */
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};
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#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
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@ -126,6 +126,8 @@ extern int free_irte(int irq);
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extern int irq_remapped(int irq);
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extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
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extern struct intel_iommu *map_ioapic_to_ir(int apic);
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extern int set_ioapic_sid(struct irte *irte, int apic);
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extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
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#else
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static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
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{
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@ -156,6 +158,15 @@ static inline struct intel_iommu *map_ioapic_to_ir(int apic)
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{
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return NULL;
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}
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static inline int set_ioapic_sid(struct irte *irte, int apic)
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{
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return 0;
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}
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static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
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{
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return 0;
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}
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#define irq_remapped(irq) (0)
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#define enable_intr_remapping(mode) (-1)
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#define disable_intr_remapping() (0)
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