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ixgbe: Correct spec violations by waiting after reset
The ixgbe driver was violating the specification in the datasheet by not waiting 1ms before checking for the reset bit clearing. This is called out for devices supported by ixgbe, so implement the required delay. Reported-by: Dan Streetman <dan.streetman@canonical.com> Signed-off-by: Mark Rustad <mark.d.rustad@intel.com> Tested-by: Darin Miller <darin.j.miller@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -1,7 +1,7 @@
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2014 Intel Corporation.
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Copyright(c) 1999 - 2015 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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@ -765,13 +765,14 @@ mac_reset_top:
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ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
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IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
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IXGBE_WRITE_FLUSH(hw);
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usleep_range(1000, 1200);
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/* Poll for reset bit to self-clear indicating reset is complete */
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for (i = 0; i < 10; i++) {
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udelay(1);
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ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
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if (!(ctrl & IXGBE_CTRL_RST))
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break;
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udelay(1);
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}
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if (ctrl & IXGBE_CTRL_RST) {
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status = IXGBE_ERR_RESET_FAILED;
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@ -990,13 +990,14 @@ mac_reset_top:
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ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
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IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
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IXGBE_WRITE_FLUSH(hw);
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usleep_range(1000, 1200);
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/* Poll for reset bit to self-clear indicating reset is complete */
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for (i = 0; i < 10; i++) {
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udelay(1);
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ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
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if (!(ctrl & IXGBE_CTRL_RST_MASK))
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break;
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udelay(1);
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}
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if (ctrl & IXGBE_CTRL_RST_MASK) {
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@ -110,13 +110,14 @@ mac_reset_top:
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ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
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IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
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IXGBE_WRITE_FLUSH(hw);
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usleep_range(1000, 1200);
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/* Poll for reset bit to self-clear indicating reset is complete */
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for (i = 0; i < 10; i++) {
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udelay(1);
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ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
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if (!(ctrl & IXGBE_CTRL_RST_MASK))
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break;
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udelay(1);
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}
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if (ctrl & IXGBE_CTRL_RST_MASK) {
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@ -2146,13 +2146,14 @@ mac_reset_top:
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ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
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IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
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IXGBE_WRITE_FLUSH(hw);
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usleep_range(1000, 1200);
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/* Poll for reset bit to self-clear meaning reset is complete */
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for (i = 0; i < 10; i++) {
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udelay(1);
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ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
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if (!(ctrl & IXGBE_CTRL_RST_MASK))
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break;
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udelay(1);
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}
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if (ctrl & IXGBE_CTRL_RST_MASK) {
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