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m68k: Fix misspellings in comments.

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Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Acked-by: Greg Ungerer <gerg@uclinux.org> [nommu, coldfire]
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
This commit is contained in:
Adam Buchbinder 2016-02-25 09:53:55 -08:00 committed by Geert Uytterhoeven
parent a95517992a
commit efbec135f1
7 changed files with 14 additions and 14 deletions
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6
arch/m68k/include/asm/MC68328.h
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@ -798,7 +798,7 @@
/**********
*
* 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS)
* 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
*
**********/
@ -824,7 +824,7 @@
/**********
*
* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
*
**********/
@ -904,7 +904,7 @@
#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT 0
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT 8
#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
#define UBAUD_GPIOSRC 0x1000 /* GPIO source */

6
arch/m68k/include/asm/MC68EZ328.h
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@ -631,7 +631,7 @@
/**********
*
* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
*
**********/
@ -712,7 +712,7 @@
#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT 0
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT 8
#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
@ -1160,7 +1160,7 @@ typedef volatile struct {
#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
#define DRAMMC_REF_SHIFT 0
/*

6
arch/m68k/include/asm/MC68VZ328.h
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@ -724,7 +724,7 @@
/**********
*
* 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM)
* 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
*
**********/
@ -806,7 +806,7 @@
#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */
#define UBAUD_PRESCALER_SHIFT 0
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */
#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divisor */
#define UBAUD_DIVIDE_SHIFT 8
#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */
#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */
@ -1256,7 +1256,7 @@ typedef struct {
#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */
#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */
#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */
#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */
#define DRAMMC_REF_MASK 0x001f /* Refresh Cycle */
#define DRAMMC_REF_SHIFT 0
/*

4
arch/m68k/include/asm/m54xxacr.h
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@ -23,8 +23,8 @@
#define CACR_IEC 0x00008000 /* Enable instruction cache */
#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */
#define CACR_IDPI 0x00001000 /* Disable CPUSHL */
#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */
#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */
#define CACR_IHLCK 0x00000800 /* Instruction cache half lock */
#define CACR_IDCM 0x00000400 /* Instruction cache inhibit */
#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */
#define CACR_EUSP 0x00000020 /* Enable separate user a7 */

2
arch/m68k/include/asm/mac_iop.h
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@ -48,7 +48,7 @@
/* IOP message status codes */
#define IOP_MSGSTATUS_UNUSED 0 /* Unusued message structure */
#define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */
#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */
#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */
#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */

2
arch/m68k/include/asm/mcftimer.h
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@ -51,7 +51,7 @@
* Bit definitions for the Timer Event Registers (TER).
*/
#define MCFTIMER_TER_CAP 0x01 /* Capture event */
#define MCFTIMER_TER_REF 0x02 /* Refernece event */
#define MCFTIMER_TER_REF 0x02 /* Reference event */
/****************************************************************************/
#endif /* mcftimer_h */

2
arch/m68k/mac/via.c
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@ -68,7 +68,7 @@ static int gIER,gIFR,gBufA,gBufB;
* interrupt. This limitation also seems to apply to VIA clone logic cores in
* Quadra-like ASICs. (RBV and OSS machines don't have this limitation.)
*
* We used to fake it by configuring the relevent VIA pin as an output
* We used to fake it by configuring the relevant VIA pin as an output
* (to mask the interrupt) or input (to unmask). That scheme did not work on
* (at least) the Quadra 700. A NuBus card's /NMRQ signal is an open-collector
* circuit (see Designing Cards and Drivers for Macintosh II and Macintosh SE,