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ARM: dts: Put Cygnus core components under core bus
Put all Cygnus core components into "core" node of type "simple-bus" in bcm-cygnus.dtsi Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -58,6 +58,36 @@
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/include/ "bcm-cygnus-clock.dtsi"
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core {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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pinctrl: pinctrl@0x0301d0c8 {
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compatible = "brcm,cygnus-pinmux";
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reg = <0x0301d0c8 0x30>,
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@ -227,28 +257,4 @@
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brcm,nand-has-wp;
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};
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gic: interrupt-controller@19021000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x19021000 0x1000>,
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<0x19020100 0x100>;
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};
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L2: l2-cache {
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compatible = "arm,pl310-cache";
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reg = <0x19022000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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timer@19020200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x19020200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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};
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