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ARM: dts: sunxi: Add all CPUs in cooling maps

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Each CPU can (and does) participate in cooling down the system but the
DT only captures a handful of them, normally CPU0, in the cooling maps.
Things work by chance currently as under normal circumstances its the
first CPU of each cluster which is used by the operating systems to
probe the cooling devices. But as soon as this CPU ordering changes and
any other CPU is used to bring up the cooling device, we will start
seeing failures.

Also the DT is rather incomplete when we list only one CPU in the
cooling maps, as the hardware doesn't have any such limitations.

Update cooling maps to include all devices affected by individual trip
points.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Viresh Kumar 2018-11-16 15:31:14 +05:30 committed by Maxime Ripard
parent a63ea49a65
commit ef47345004
No known key found for this signature in database
GPG Key ID: E3EF0D6F671851C5
3 changed files with 21 additions and 11 deletions
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11
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -115,7 +115,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@1 { cpu1: cpu@1 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
@ -131,7 +131,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@2 { cpu2: cpu@2 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
@ -147,7 +147,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@3 { cpu3: cpu@3 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
@ -174,7 +174,10 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu_alert0>; trip = <&cpu_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };

5
arch/arm/boot/dts/sun7i-a20.dtsi
View File

@ -118,7 +118,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@1 { cpu1: cpu@1 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
@ -148,7 +148,8 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu_alert0>; trip = <&cpu_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
}; };

16
arch/arm/boot/dts/sun8i-a33.dtsi
View File

@ -131,14 +131,14 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@1 { cpu1: cpu@1 {
clocks = <&ccu CLK_CPUX>; clocks = <&ccu CLK_CPUX>;
clock-names = "cpu"; clock-names = "cpu";
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@2 { cpu2: cpu@2 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <2>; reg = <2>;
@ -148,7 +148,7 @@
#cooling-cells = <2>; #cooling-cells = <2>;
}; };
cpu@3 { cpu3: cpu@3 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <3>; reg = <3>;
@ -479,11 +479,17 @@
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu_alert0>; trip = <&cpu_alert0>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map1 { map1 {
trip = <&cpu_alert1>; trip = <&cpu_alert1>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
}; };
map2 { map2 {