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powerpc: add documentation for HWCAPs
Take the arm64 HWCAP documentation file and adjust it for powerpc. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org> [mpe: Fix ARCH_2_05 comment, as noticed by Tulio.] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220715012636.165948-1-npiggin@gmail.com
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Nicholas Piggin
Michael Ellerman
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234
Documentation/powerpc/elf_hwcaps.rst
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234
Documentation/powerpc/elf_hwcaps.rst
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.. _elf_hwcaps_index:
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==================
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POWERPC ELF HWCAPs
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==================
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This document describes the usage and semantics of the powerpc ELF HWCAPs.
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1. Introduction
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---------------
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Some hardware or software features are only available on some CPU
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implementations, and/or with certain kernel configurations, but have no other
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discovery mechanism available to userspace code. The kernel exposes the
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presence of these features to userspace through a set of flags called HWCAPs,
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exposed in the auxiliary vector.
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Userspace software can test for features by acquiring the AT_HWCAP or
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AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
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flags are set, e.g.::
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bool floating_point_is_present(void)
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{
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unsigned long HWCAPs = getauxval(AT_HWCAP);
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if (HWCAPs & PPC_FEATURE_HAS_FPU)
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return true;
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return false;
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}
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Where software relies on a feature described by a HWCAP, it should check the
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relevant HWCAP flag to verify that the feature is present before attempting to
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make use of the feature.
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HWCAP is the preferred method to test for the presence of a feature rather
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than probing through other means, which may not be reliable or may cause
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unpredictable behaviour.
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Software that targets a particular platform does not necessarily have to
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test for required or implied features. For example if the program requires
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FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be
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impossible to do so if the compiler generates code requiring those features.
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2. Facilities
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-------------
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The Power ISA uses the term "facility" to describe a class of instructions,
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registers, interrupts, etc. The presence or absence of a facility indicates
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whether this class is available to be used, but the specifics depend on the
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ISA version. For example, if the VSX facility is available, the VSX
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instructions that can be used differ between the v3.0B and v3.1B ISA
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versions.
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3. Categories
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-------------
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The Power ISA before v3.0 uses the term "category" to describe certain
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classes of instructions and operating modes which may be optional or
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mutually exclusive, the exact meaning of the HWCAP flag may depend on
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context, e.g., the presence of the BOOKE feature implies that the server
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category is not implemented.
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4. HWCAP allocation
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-------------------
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HWCAPs are allocated as described in Power Architecture 64-Bit ELF V2 ABI
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Specification (which will be reflected in the kernel's uapi headers).
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5. The HWCAPs exposed in AT_HWCAP
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---------------------------------
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PPC_FEATURE_32
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32-bit CPU
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PPC_FEATURE_64
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64-bit CPU (userspace may be running in 32-bit mode).
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PPC_FEATURE_601_INSTR
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The processor is PowerPC 601.
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Unused in the kernel since:
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f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
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PPC_FEATURE_HAS_ALTIVEC
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Vector (aka Altivec, VMX) facility is available.
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PPC_FEATURE_HAS_FPU
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Floating point facility is available.
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PPC_FEATURE_HAS_MMU
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Memory management unit is present and enabled.
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PPC_FEATURE_HAS_4xxMAC
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The processor is 40x or 44x family.
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PPC_FEATURE_UNIFIED_CACHE
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The processor has a unified L1 cache for instructions and data, as
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found in NXP e200.
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Unused in the kernel since:
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39c8bf2b3cc1 ("powerpc: Retire e200 core (mpc555x processor)")
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PPC_FEATURE_HAS_SPE
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Signal Processing Engine facility is available.
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PPC_FEATURE_HAS_EFP_SINGLE
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Embedded Floating Point single precision operations are available.
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PPC_FEATURE_HAS_EFP_DOUBLE
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Embedded Floating Point double precision operations are available.
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PPC_FEATURE_NO_TB
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The timebase facility (mftb instruction) is not available.
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This is a 601 specific HWCAP, so if it is known that the processor
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running is not a 601, via other HWCAPs or other means, it is not
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required to test this bit before using the timebase.
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Unused in the kernel since:
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f0ed73f3fa2c ("powerpc: Remove PowerPC 601")
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PPC_FEATURE_POWER4
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The processor is POWER4 or PPC970/FX/MP.
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POWER4 support dropped from the kernel since:
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471d7ff8b51b ("powerpc/64s: Remove POWER4 support")
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PPC_FEATURE_POWER5
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The processor is POWER5.
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PPC_FEATURE_POWER5_PLUS
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The processor is POWER5+.
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PPC_FEATURE_CELL
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The processor is Cell.
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PPC_FEATURE_BOOKE
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The processor implements the embedded category ("BookE") architecture.
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PPC_FEATURE_SMT
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The processor implements SMT.
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PPC_FEATURE_ICACHE_SNOOP
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The processor icache is coherent with the dcache, and instruction storage
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can be made consistent with data storage for the purpose of executing
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instructions with the sequence (as described in, e.g., POWER9 Processor
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User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)):
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sync
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icbi (to any address)
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isync
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PPC_FEATURE_ARCH_2_05
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The processor supports the v2.05 userlevel architecture. Processors
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supporting later architectures DO NOT set this feature.
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PPC_FEATURE_PA6T
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The processor is PA6T.
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PPC_FEATURE_HAS_DFP
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DFP facility is available.
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PPC_FEATURE_POWER6_EXT
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The processor is POWER6.
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PPC_FEATURE_ARCH_2_06
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The processor supports the v2.06 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE_HAS_VSX
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VSX facility is available.
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PPC_FEATURE_PSERIES_PERFMON_COMPAT
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The processor supports architected PMU events in the range 0xE0-0xFF.
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PPC_FEATURE_TRUE_LE
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The processor supports true little-endian mode.
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PPC_FEATURE_PPC_LE
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The processor supports "PowerPC Little-Endian", that uses address
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munging to make storage access appear to be little-endian, but the
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data is stored in a different format that is unsuitable to be
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accessed by other agents not running in this mode.
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6. The HWCAPs exposed in AT_HWCAP2
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----------------------------------
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PPC_FEATURE2_ARCH_2_07
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The processor supports the v2.07 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_HTM
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Transactional Memory feature is available.
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PPC_FEATURE2_DSCR
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DSCR facility is available.
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PPC_FEATURE2_EBB
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EBB facility is available.
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PPC_FEATURE2_ISEL
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isel instruction is available. This is superseded by ARCH_2_07 and
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later.
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PPC_FEATURE2_TAR
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TAR facility is available.
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PPC_FEATURE2_VEC_CRYPTO
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v2.07 crypto instructions are available.
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PPC_FEATURE2_HTM_NOSC
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System calls fail if called in a transactional state, see
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Documentation/powerpc/syscall64-abi.rst
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PPC_FEATURE2_ARCH_3_00
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The processor supports the v3.0B / v3.0C userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_HAS_IEEE128
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IEEE 128-bit binary floating point is supported with VSX
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quad-precision instructions and data types.
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PPC_FEATURE2_DARN
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darn instruction is available.
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PPC_FEATURE2_SCV
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The scv 0 instruction may be used for system calls, see
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Documentation/powerpc/syscall64-abi.rst.
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PPC_FEATURE2_HTM_NO_SUSPEND
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A limited Transactional Memory facility that does not support suspend is
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available, see Documentation/powerpc/transactional_memory.rst.
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PPC_FEATURE2_ARCH_3_1
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The processor supports the v3.1 userlevel architecture. Processors
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supporting later architectures also set this feature.
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PPC_FEATURE2_MMA
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MMA facility is available.
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