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powerpc: Add VMX optimised xor for RAID5
Add a VMX optimised xor, used primarily for RAID5. On a POWER7 blade this is a decent win: 32regs : 17932.800 MB/sec altivec : 19724.800 MB/sec The bigger gain is when the same test is run in SMT4 mode, as it would if there was a lot of work going on: 8regs : 8377.600 MB/sec altivec : 15801.600 MB/sec I tested this against an array created without the patch, and also verified it worked as expected on a little endian kernel. [ Fix !CONFIG_ALTIVEC build -- BenH ] Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Anton Blanchard
Benjamin Herrenschmidt
parent
07fb41a752
commit
ef1313deaf
@ -1 +1,68 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#ifndef _ASM_POWERPC_XOR_H
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#define _ASM_POWERPC_XOR_H
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#ifdef CONFIG_ALTIVEC
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#include <asm/cputable.h>
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void xor_altivec_2(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in);
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void xor_altivec_3(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in);
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void xor_altivec_4(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in,
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unsigned long *v4_in);
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void xor_altivec_5(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in,
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unsigned long *v4_in, unsigned long *v5_in);
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static struct xor_block_template xor_block_altivec = {
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.name = "altivec",
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.do_2 = xor_altivec_2,
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.do_3 = xor_altivec_3,
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.do_4 = xor_altivec_4,
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.do_5 = xor_altivec_5,
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};
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#define XOR_SPEED_ALTIVEC() \
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do { \
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if (cpu_has_feature(CPU_FTR_ALTIVEC)) \
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xor_speed(&xor_block_altivec); \
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} while (0)
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#else
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#define XOR_SPEED_ALTIVEC()
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#endif
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/* Also try the generic routines. */
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#include <asm-generic/xor.h>
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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xor_speed(&xor_block_8regs); \
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xor_speed(&xor_block_8regs_p); \
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xor_speed(&xor_block_32regs); \
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xor_speed(&xor_block_32regs_p); \
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XOR_SPEED_ALTIVEC(); \
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} while (0)
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#endif /* _ASM_POWERPC_XOR_H */
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@ -39,3 +39,6 @@ obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o
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obj-y += code-patching.o
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obj-y += feature-fixups.o
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obj-$(CONFIG_FTR_FIXUP_SELFTEST) += feature-fixups-test.o
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obj-$(CONFIG_ALTIVEC) += xor_vmx.o
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CFLAGS_xor_vmx.o += -maltivec -mabi=altivec
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177
arch/powerpc/lib/xor_vmx.c
Normal file
177
arch/powerpc/lib/xor_vmx.c
Normal file
@ -0,0 +1,177 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2012
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*
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* Author: Anton Blanchard <anton@au.ibm.com>
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*/
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#include <altivec.h>
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#include <linux/preempt.h>
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#include <linux/export.h>
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#include <linux/sched.h>
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#include <asm/switch_to.h>
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typedef vector signed char unative_t;
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#define DEFINE(V) \
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unative_t *V = (unative_t *)V##_in; \
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unative_t V##_0, V##_1, V##_2, V##_3
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#define LOAD(V) \
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do { \
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V##_0 = V[0]; \
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V##_1 = V[1]; \
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V##_2 = V[2]; \
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V##_3 = V[3]; \
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} while (0)
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#define STORE(V) \
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do { \
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V[0] = V##_0; \
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V[1] = V##_1; \
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V[2] = V##_2; \
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V[3] = V##_3; \
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} while (0)
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#define XOR(V1, V2) \
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do { \
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V1##_0 = vec_xor(V1##_0, V2##_0); \
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V1##_1 = vec_xor(V1##_1, V2##_1); \
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V1##_2 = vec_xor(V1##_2, V2##_2); \
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V1##_3 = vec_xor(V1##_3, V2##_3); \
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} while (0)
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void xor_altivec_2(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in)
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{
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DEFINE(v1);
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DEFINE(v2);
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unsigned long lines = bytes / (sizeof(unative_t)) / 4;
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preempt_disable();
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enable_kernel_altivec();
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do {
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LOAD(v1);
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LOAD(v2);
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XOR(v1, v2);
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STORE(v1);
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v1 += 4;
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v2 += 4;
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} while (--lines > 0);
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preempt_enable();
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}
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EXPORT_SYMBOL(xor_altivec_2);
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void xor_altivec_3(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in)
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{
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DEFINE(v1);
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DEFINE(v2);
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DEFINE(v3);
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unsigned long lines = bytes / (sizeof(unative_t)) / 4;
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preempt_disable();
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enable_kernel_altivec();
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do {
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LOAD(v1);
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LOAD(v2);
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LOAD(v3);
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XOR(v1, v2);
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XOR(v1, v3);
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STORE(v1);
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v1 += 4;
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v2 += 4;
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v3 += 4;
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} while (--lines > 0);
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preempt_enable();
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}
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EXPORT_SYMBOL(xor_altivec_3);
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void xor_altivec_4(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in,
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unsigned long *v4_in)
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{
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DEFINE(v1);
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DEFINE(v2);
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DEFINE(v3);
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DEFINE(v4);
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unsigned long lines = bytes / (sizeof(unative_t)) / 4;
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preempt_disable();
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enable_kernel_altivec();
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do {
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LOAD(v1);
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LOAD(v2);
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LOAD(v3);
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LOAD(v4);
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XOR(v1, v2);
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XOR(v3, v4);
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XOR(v1, v3);
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STORE(v1);
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v1 += 4;
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v2 += 4;
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v3 += 4;
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v4 += 4;
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} while (--lines > 0);
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preempt_enable();
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}
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EXPORT_SYMBOL(xor_altivec_4);
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void xor_altivec_5(unsigned long bytes, unsigned long *v1_in,
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unsigned long *v2_in, unsigned long *v3_in,
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unsigned long *v4_in, unsigned long *v5_in)
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{
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DEFINE(v1);
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DEFINE(v2);
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DEFINE(v3);
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DEFINE(v4);
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DEFINE(v5);
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unsigned long lines = bytes / (sizeof(unative_t)) / 4;
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preempt_disable();
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enable_kernel_altivec();
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do {
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LOAD(v1);
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LOAD(v2);
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LOAD(v3);
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LOAD(v4);
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LOAD(v5);
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XOR(v1, v2);
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XOR(v3, v4);
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XOR(v1, v5);
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XOR(v1, v3);
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STORE(v1);
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v1 += 4;
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v2 += 4;
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v3 += 4;
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v4 += 4;
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v5 += 4;
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} while (--lines > 0);
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preempt_enable();
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}
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EXPORT_SYMBOL(xor_altivec_5);
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