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arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. General features: - NXP i.MX8M Plus - Up to 4GB LDDR4 - 8 eMMC - Gigabit Ethernet - USB 3.0, 2.0 Host/OTG - PCIe 3.0 interface - I2S - LVDS - rest of i.MX8M Plus features i.Core MX8M Plus needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com> Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Manoj Sai
Shawn Guo
parent
e55264f3d7
commit
eefe06b295
186
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
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186
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 NXP
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* Copyright (c) 2019 Engicam srl
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* Copyright (c) 2020 Amarula Solutons(India)
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*/
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/ {
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compatible = "engicam,icore-mx8mp", "fsl,imx8mp";
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pca9450: pmic@25 {
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compatible = "nxp,pca9450c";
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interrupt-parent = <&gpio3>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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reg = <0x25>;
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regulators {
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buck1: BUCK1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <720000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "BUCK1";
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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nxp,dvs-run-voltage = <950000>;
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nxp,dvs-standby-voltage = <850000>;
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1025000>;
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regulator-min-microvolt = <720000>;
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regulator-name = "BUCK2";
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3600000>;
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regulator-min-microvolt = <3000000>;
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regulator-name = "BUCK4";
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};
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buck5: BUCK5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1950000>;
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regulator-min-microvolt = <1650000>;
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regulator-name = "BUCK5";
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};
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buck6: BUCK6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1155000>;
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regulator-min-microvolt = <1045000>;
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regulator-name = "BUCK6";
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};
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ldo1: LDO1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1950000>;
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regulator-min-microvolt = <1650000>;
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regulator-name = "LDO1";
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};
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ldo3: LDO3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <1890000>;
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regulator-min-microvolt = <1710000>;
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regulator-name = "LDO3";
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};
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ldo5: LDO5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-max-microvolt = <3300000>;
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regulator-min-microvolt = <1800000>;
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regulator-name = "LDO5";
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};
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};
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};
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};
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/* EMMC */
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&usdhc3 {
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bus-width = <8>;
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non-removable;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
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MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_pmic: pmicgrp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
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MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
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MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
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MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
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MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
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MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
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MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
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>;
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};
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};
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