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drm/pl111: Support variants with broken clock divider
The early Integrator CLCD synthesized in the Integrator CP and IM-PD1 FPGAs are broken: their clock dividers do not work properly. Support disabling the clock divider and drive the clock directly from the parent under these circumstances. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180206093540.8147-3-linus.walleij@linaro.org
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@ -138,6 +138,9 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
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tim2 = readl(priv->regs + CLCD_TIM2);
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tim2 &= (TIM2_BCD | TIM2_PCD_LO_MASK | TIM2_PCD_HI_MASK);
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if (priv->variant->broken_clockdivider)
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tim2 |= TIM2_BCD;
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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tim2 |= TIM2_IHS;
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@ -455,6 +458,11 @@ pl111_init_clock_divider(struct drm_device *drm)
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dev_err(drm->dev, "CLCD: unable to get clcdclk.\n");
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return PTR_ERR(parent);
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}
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/* If the clock divider is broken, use the parent directly */
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if (priv->variant->broken_clockdivider) {
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priv->clk = parent;
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return 0;
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}
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parent_name = __clk_get_name(parent);
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spin_lock_init(&priv->tim2_lock);
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@ -38,6 +38,8 @@ struct drm_minor;
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* @is_pl110: this is the early PL110 variant
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* @external_bgr: this is the Versatile Pl110 variant with external
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* BGR/RGB routing
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* @broken_clockdivider: the clock divider is broken and we need to
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* use the supplied clock directly
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* @formats: array of supported pixel formats on this variant
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* @nformats: the length of the array of supported pixel formats
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*/
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@ -45,6 +47,7 @@ struct pl111_variant_data {
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const char *name;
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bool is_pl110;
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bool external_bgr;
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bool broken_clockdivider;
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const u32 *formats;
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unsigned int nformats;
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};
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@ -237,6 +237,7 @@ static const u32 pl110_versatile_pixel_formats[] = {
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static const struct pl111_variant_data pl110_integrator = {
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.name = "PL110 Integrator",
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.is_pl110 = true,
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.broken_clockdivider = true,
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.formats = pl110_integrator_pixel_formats,
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.nformats = ARRAY_SIZE(pl110_integrator_pixel_formats),
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};
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