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ata: sata_dwc_460ex: use readl/writel_relaxed()
Rename the register access macros and use standard _relaxed() ops instead of __raw variants with explicit byte swapping. The original driver used the ppc-specific in/out_le32(). When it was adapted to other systems, these were added to the driver under ifdefs. However, those names are not defined as macros on ppc, so it ended up replacing them there as well with altered semantics. This patch restores the original semantics on ppc and makes the accesses no less strict on other systems. Also fixes too many sparse warnings to count. Tested-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Mans Rullgard
Tejun Heo
parent
9e8b855e98
commit
ee81d6cc8e
@ -51,13 +51,8 @@
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#define DRV_NAME "sata-dwc"
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#define DRV_VERSION "1.3"
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#ifndef out_le32
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#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
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#endif
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#ifndef in_le32
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#define in_le32(a) __le32_to_cpu(__raw_readl((void __iomem *)(a)))
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#endif
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#define sata_dwc_writel(a, v) writel_relaxed(v, a)
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#define sata_dwc_readl(a) readl_relaxed(a)
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#ifndef NO_IRQ
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#define NO_IRQ 0
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@ -425,7 +420,7 @@ static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
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return -EINVAL;
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}
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*val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4));
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*val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
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dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
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__func__, link->ap->print_id, scr, *val);
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@ -441,7 +436,7 @@ static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
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__func__, scr);
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return -EINVAL;
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}
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out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val);
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sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
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return 0;
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}
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@ -455,8 +450,8 @@ static void clear_serror(struct ata_port *ap)
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static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
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{
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out_le32(&hsdev->sata_dwc_regs->intpr,
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in_le32(&hsdev->sata_dwc_regs->intpr));
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sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
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sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
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}
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static u32 qcmd_tag_to_mask(u8 tag)
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@ -532,7 +527,7 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
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spin_lock_irqsave(&host->lock, flags);
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/* Read the interrupt register */
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intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
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intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
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ap = host->ports[port];
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hsdevp = HSDEVP_FROM_AP(ap);
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@ -551,7 +546,7 @@ static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
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if (intpr & SATA_DWC_INTPR_NEWFP) {
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clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
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tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
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tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
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dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
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if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
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dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
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@ -736,13 +731,13 @@ static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
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struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
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if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
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out_le32(&(hsdev->sata_dwc_regs->dmacr),
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SATA_DWC_DMACR_RX_CLEAR(
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in_le32(&(hsdev->sata_dwc_regs->dmacr))));
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_RX_CLEAR(
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sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr)));
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} else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
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out_le32(&(hsdev->sata_dwc_regs->dmacr),
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SATA_DWC_DMACR_TX_CLEAR(
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in_le32(&(hsdev->sata_dwc_regs->dmacr))));
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TX_CLEAR(
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sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr)));
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} else {
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/*
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* This should not happen, it indicates the driver is out of
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@ -751,9 +746,9 @@ static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
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dev_err(hsdev->dev,
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"%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
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__func__, tag, hsdevp->dma_pending[tag],
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in_le32(&hsdev->sata_dwc_regs->dmacr));
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out_le32(&(hsdev->sata_dwc_regs->dmacr),
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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}
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}
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@ -778,7 +773,7 @@ static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
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__func__, qc->tag, qc->tf.command,
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get_dma_dir_descript(qc->dma_dir),
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get_prot_descript(qc->tf.protocol),
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in_le32(&(hsdev->sata_dwc_regs->dmacr)));
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sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
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}
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#endif
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@ -787,7 +782,7 @@ static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
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dev_err(ap->dev,
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"%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
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__func__,
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in_le32(&(hsdev->sata_dwc_regs->dmacr)));
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sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
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}
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hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
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@ -828,20 +823,20 @@ static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
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static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
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{
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/* Enable selective interrupts by setting the interrupt maskregister*/
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out_le32(&hsdev->sata_dwc_regs->intmr,
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SATA_DWC_INTMR_ERRM |
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SATA_DWC_INTMR_NEWFPM |
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SATA_DWC_INTMR_PMABRTM |
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SATA_DWC_INTMR_DMATM);
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sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
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SATA_DWC_INTMR_ERRM |
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SATA_DWC_INTMR_NEWFPM |
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SATA_DWC_INTMR_PMABRTM |
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SATA_DWC_INTMR_DMATM);
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/*
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* Unmask the error bits that should trigger an error interrupt by
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* setting the error mask register.
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*/
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out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
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sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
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dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
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__func__, in_le32(&hsdev->sata_dwc_regs->intmr),
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in_le32(&hsdev->sata_dwc_regs->errmr));
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__func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
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sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
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}
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static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
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@ -938,14 +933,14 @@ static int sata_dwc_port_start(struct ata_port *ap)
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if (ap->port_no == 0) {
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dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
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__func__);
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out_le32(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
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__func__);
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out_le32(&hsdev->sata_dwc_regs->dbtsr,
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(SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
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SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
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sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
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(SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
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SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
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}
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/* Clear any error bits before libata starts issuing commands */
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@ -1060,11 +1055,11 @@ static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
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}
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if (dir == DMA_TO_DEVICE)
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out_le32(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXCHEN);
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXCHEN);
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else
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out_le32(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_RXCHEN);
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_RXCHEN);
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/* Enable AHB DMA transfer on the specified channel */
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dmaengine_submit(desc);
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@ -1148,13 +1143,13 @@ static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
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sata_dwc_enable_interrupts(hsdev);
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/* Reconfigure the DMA control register */
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out_le32(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
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SATA_DWC_DMACR_TXRXCH_CLEAR);
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/* Reconfigure the DMA Burst Transaction Size register */
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out_le32(&hsdev->sata_dwc_regs->dbtsr,
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SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
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SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
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sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
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SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
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SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
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return ret;
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}
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@ -1254,8 +1249,8 @@ static int sata_dwc_probe(struct platform_device *ofdev)
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sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
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/* Read the ID and Version Registers */
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idr = in_le32(&hsdev->sata_dwc_regs->idr);
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versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
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idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
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versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
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dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
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idr, ver[0], ver[1], ver[2]);
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