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clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

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DSI DPHY gate bit on MIPI DSI clock register is bit 15
not bit 30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Jagan Teki 2018-11-13 16:46:08 +05:30 committed by Maxime Ripard
parent 7d3cf7d2ec
commit ee678706e4
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 1 additions and 1 deletions
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drivers/clk/sunxi-ng/ccu-sun50i-a64.c
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@ -586,7 +586,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
static const u8 dsi_dphy_table[] = { 0, 2, }; static const u8 dsi_dphy_table[] = { 0, 2, };
static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
dsi_dphy_parents, dsi_dphy_table, dsi_dphy_parents, dsi_dphy_table,
0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT); 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);