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ath5k: Wakeup fixes
* Don't put chip to full sleep because there are problems during wakeup. Instead hold MAC/Baseband on warm reset state via a new function ath5k_hw_on_hold. * Minor cleanups Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Tested-by: Ben Greear <greearb@candelatech.com> Tested-by: Johannes Stezenbach <js@sig21.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -1157,6 +1157,7 @@ extern void ath5k_unregister_leds(struct ath5k_softc *sc);
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/* Reset Functions */
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extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
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extern int ath5k_hw_on_hold(struct ath5k_hw *ah);
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extern int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, struct ieee80211_channel *channel, bool change_channel);
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/* Power management functions */
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extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, bool set_chip, u16 sleep_duration);
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@ -145,7 +145,7 @@ struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
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goto err_free;
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/* Bring device out of sleep and reset it's units */
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ret = ath5k_hw_nic_wakeup(ah, CHANNEL_B, true);
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ret = ath5k_hw_nic_wakeup(ah, 0, true);
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if (ret)
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goto err_free;
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@ -2446,27 +2446,29 @@ ath5k_stop_hw(struct ath5k_softc *sc)
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ret = ath5k_stop_locked(sc);
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if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
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/*
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* Set the chip in full sleep mode. Note that we are
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* careful to do this only when bringing the interface
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* completely to a stop. When the chip is in this state
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* it must be carefully woken up or references to
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* registers in the PCI clock domain may freeze the bus
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* (and system). This varies by chip and is mostly an
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* issue with newer parts that go to sleep more quickly.
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*/
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if (sc->ah->ah_mac_srev >= 0x78) {
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/*
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* XXX
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* don't put newer MAC revisions > 7.8 to sleep because
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* of the above mentioned problems
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*/
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ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
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"not putting device to sleep\n");
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} else {
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ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
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"putting device to full sleep\n");
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ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
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}
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* Don't set the card in full sleep mode!
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*
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* a) When the device is in this state it must be carefully
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* woken up or references to registers in the PCI clock
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* domain may freeze the bus (and system). This varies
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* by chip and is mostly an issue with newer parts
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* (madwifi sources mentioned srev >= 0x78) that go to
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* sleep more quickly.
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*
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* b) On older chips full sleep results a weird behaviour
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* during wakeup. I tested various cards with srev < 0x78
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* and they don't wake up after module reload, a second
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* module reload is needed to bring the card up again.
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*
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* Until we figure out what's going on don't enable
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* full chip reset on any chip (this is what Legacy HAL
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* and Sam's HAL do anyway). Instead Perform a full reset
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* on the device (same as initial state after attach) and
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* leave it idle (keep MAC/BB on warm reset) */
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ret = ath5k_hw_on_hold(sc->ah);
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ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
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"putting device to sleep\n");
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}
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ath5k_txbuf_free(sc, sc->bbuf);
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@ -258,29 +258,35 @@ int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
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if (!set_chip)
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goto commit;
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/* Preserve sleep duration */
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data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);
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/* If card is down we 'll get 0xffff... so we
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* need to clean this up before we write the register
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*/
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if (data & 0xffc00000)
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data = 0;
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else
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data = data & 0xfffcffff;
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/* Preserve sleep duration etc */
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data = data & ~AR5K_SLEEP_CTL_SLE;
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ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
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ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
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AR5K_SLEEP_CTL);
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udelay(15);
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for (i = 50; i > 0; i--) {
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for (i = 200; i > 0; i--) {
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/* Check if the chip did wake up */
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if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
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AR5K_PCICFG_SPWR_DN) == 0)
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break;
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/* Wait a bit and retry */
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udelay(200);
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ath5k_hw_reg_write(ah, data, AR5K_SLEEP_CTL);
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udelay(50);
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ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,
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AR5K_SLEEP_CTL);
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}
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/* Fail if the chip didn't wake up */
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if (i <= 0)
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if (i == 0)
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return -EIO;
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break;
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@ -295,6 +301,64 @@ commit:
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return 0;
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}
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/*
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* Put device on hold
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*
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* Put MAC and Baseband on warm reset and
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* keep that state (don't clean sleep control
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* register). After this MAC and Baseband are
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* disabled and a full reset is needed to come
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* back. This way we save as much power as possible
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* without puting the card on full sleep.
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*/
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int ath5k_hw_on_hold(struct ath5k_hw *ah)
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{
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struct pci_dev *pdev = ah->ah_sc->pdev;
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u32 bus_flags;
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int ret;
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/* Make sure device is awake */
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
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return ret;
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}
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/*
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* Put chipset on warm reset...
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*
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* Note: puting PCI core on warm reset on PCI-E cards
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* results card to hang and always return 0xffff... so
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* we ingore that flag for PCI-E cards. On PCI cards
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* this flag gets cleared after 64 PCI clocks.
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*/
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bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
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if (ah->ah_version == AR5K_AR5210) {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
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AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
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mdelay(2);
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} else {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND | bus_flags);
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}
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to put device on warm reset\n");
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return -EIO;
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}
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/* ...wakeup again!*/
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to put device on hold\n");
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return ret;
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}
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return ret;
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}
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/*
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* Bring up MAC + PHY Chips and program PLL
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* TODO: Half/Quarter rate support
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@ -318,6 +382,50 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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return ret;
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}
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/*
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* Put chipset on warm reset...
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*
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* Note: puting PCI core on warm reset on PCI-E cards
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* results card to hang and always return 0xffff... so
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* we ingore that flag for PCI-E cards. On PCI cards
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* this flag gets cleared after 64 PCI clocks.
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*/
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bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
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if (ah->ah_version == AR5K_AR5210) {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
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AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
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mdelay(2);
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} else {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND | bus_flags);
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}
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
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return -EIO;
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}
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/* ...wakeup again!...*/
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
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return ret;
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}
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/* ...clear reset control register and pull device out of
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* warm reset */
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if (ath5k_hw_nic_reset(ah, 0)) {
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ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
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return -EIO;
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}
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/* On initialization skip PLL programming since we don't have
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* a channel / mode set yet */
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if (initial)
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return 0;
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if (ah->ah_version != AR5K_AR5210) {
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/*
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* Get channel mode flags
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@ -383,39 +491,6 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
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AR5K_PHY_TURBO);
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}
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/* reseting PCI on PCI-E cards results card to hang
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* and always return 0xffff... so we ingore that flag
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* for PCI-E cards */
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bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
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/* Reset chipset */
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if (ah->ah_version == AR5K_AR5210) {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
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AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
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mdelay(2);
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} else {
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ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
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AR5K_RESET_CTL_BASEBAND | bus_flags);
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}
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
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return -EIO;
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}
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/* ...wakeup again!*/
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ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
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if (ret) {
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ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
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return ret;
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}
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/* ...final warm reset */
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if (ath5k_hw_nic_reset(ah, 0)) {
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ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
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return -EIO;
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}
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if (ah->ah_version != AR5K_AR5210) {
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/* ...update PLL if needed */
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