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arm64: dts: freescale: imx93-tqma9352-mba93xxca: improve pad configuration

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- disable PU/PD if already done with external resistors
- do not configure Schmitt Trigger for outputs
- do not configure DSE / FSEL for inputs

Pad config changes suggested by hardware team.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Markus Niebel 2024-08-19 14:03:24 +02:00 committed by Shawn Guo
parent 7a47f6fa0d
commit ed02d0b9d9
1 changed files with 104 additions and 76 deletions
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180
arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts
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@ -575,22 +575,23 @@
pinctrl_eqos: eqosgrp {
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e
/* PD | FSEL_2 | DSE X6 */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
/* PD | FSEL_3 | DSE X6 */
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000
MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000
MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000
/* HYS | PD | FSEL_0 | DSE no drive */
MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e
MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
/* PD | FSEL_3 | DSE X3 */
MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
>;
@ -598,7 +599,8 @@
pinctrl_eqos_phy: eqosphygrp {
fsl,pins = <
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000
>;
};
@ -606,15 +608,16 @@
fsl,pins = <
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e
/* PD | FSEL_2 | DSE X6 */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
/* PD | FSEL_3 | DSE X6 */
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
/* SION | HYS | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000
MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000
MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000
MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000
MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000
/* HYS | PD | FSEL_0 | DSE no drive */
MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e
MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e
@ -628,44 +631,54 @@
pinctrl_fec_phy: fecphygrp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306
/* HYS | FSEL_0 | DSE no drive */
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e
MX93_PAD_PDM_CLK__CAN1_TX 0x139e
/* HYS | PU | FSEL_0 | DSE no drive */
MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200
/* PU | FSEL_3 | DSE X4 */
MX93_PAD_PDM_CLK__CAN1_TX 0x039e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
/* HYS | PU | FSEL_0 | DSE no drive */
MX93_PAD_GPIO_IO27__CAN2_RX 0x1200
/* PU | FSEL_3 | DSE X4 */
MX93_PAD_GPIO_IO25__CAN2_TX 0x039e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
/* SION | HYS | OD | FSEL_3 | DSE X4 */
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
/* SION | HYS | OD | FSEL_3 | DSE X4 */
MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e
MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e
>;
};
pinctrl_lpspi6: lpspi6grp {
fsl,pins = <
MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x3fe
MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe
MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe
MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe
/* FSEL_2 | DSE X4 */
MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x011e
/* HYS | PD | FSEL_0 | DSE no drive */
MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x1400
/* PD | FSEL_2 | DSE X4 */
MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e
MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x051e
>;
};
@ -677,13 +690,15 @@
pinctrl_pexp_irq: pexpirqgrp {
fsl,pins = <
MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306
/* HYS | FSEL_0 | No DSE */
MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1000
>;
};
pinctrl_pwmfan: pwmfangrp {
fsl,pins = <
MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1306
/* HYS | PU | FSEL_0 | no DSE */
MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1200
>;
};
@ -696,92 +711,105 @@
pinctrl_tpm5: tpm5grp {
fsl,pins = <
MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e
>;
};
pinctrl_tpm6: tpm6grp {
fsl,pins = <
MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e
MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306
/* HYS | FSEL_0 | No DSE */
MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1000
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_UART1_RXD__LPUART1_RX 0x1000
/* FSEL_2 | DSE X4 */
MX93_PAD_UART1_TXD__LPUART1_TX 0x011e
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX93_PAD_UART2_TXD__LPUART2_TX 0x31e
MX93_PAD_UART2_RXD__LPUART2_RX 0x31e
MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_UART2_RXD__LPUART2_RX 0x1000
/* FSEL_2 | DSE X4 */
MX93_PAD_UART2_TXD__LPUART2_TX 0x011e
/* FSEL_2 | DSE X4 */
MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e
MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_GPIO_IO15__LPUART3_RX 0x1000
/* FSEL_2 | DSE X4 */
MX93_PAD_GPIO_IO14__LPUART3_TX 0x011e
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e
MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_GPIO_IO05__LPUART6_RX 0x1000
/* FSEL_2 | DSE X4 */
MX93_PAD_GPIO_IO04__LPUART6_TX 0x011e
>;
};
pinctrl_uart8: uart8grp {
fsl,pins = <
MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e
MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_GPIO_IO13__LPUART8_RX 0x1000
/* FSEL_2 | DSE X4 */
MX93_PAD_GPIO_IO12__LPUART8_TX 0x011e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
/* HYS | FSEL_0 | No DSE */
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000
>;
};
pinctrl_usdhc2_hs: usdhc2hsgrp {
fsl,pins = <
/* HYS | PD | PU | FSEL_3 | DSE X5 */
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be
/* HYS | PD | PU | FSEL_3 | DSE X4 */
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
/* HYS | PD | PU | FSEL_3 | DSE X3 */
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
/* PD | PU | FSEL_2 | DSE X3 */
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
/* PD | FSEL_3 | DSE X5 */
MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be
/* HYS | PU | FSEL_3 | DSE X4 */
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
/* HYS | PU | FSEL_3 | DSE X3 */
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
/* FSEL_2 | DSE X3 */
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
>;
};
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
fsl,pins = <
/* HYS | PD | PU | FSEL_3 | DSE X6 */
MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe
/* HYS | PD | PU | FSEL_3 | DSE X4 */
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
/* PD | PU | FSEL_2 | DSE X3 */
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e
/* PD | FSEL_3 | DSE X6 */
MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe
/* HYS | PU | FSEL_3 | DSE X4 */
MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e
/* FSEL_2 | DSE X3 */
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
>;
};
};