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ASoC: tlv320aic32x4: Enable fast charge

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At power-up the analog circuits may take up to one full second before
being charged with the default configuration. Using the analog blocks
before they are ready generates a *very* crappy sound.

Enable the fast charge feature, which will require a bit more power
than normal charge but will definitely speed up the starting operation
by shrinking this delay to up to 40 ms.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20200911173140.29984-4-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Miquel Raynal 2020-09-11 19:31:40 +02:00 committed by Mark Brown
parent 40b3713628
commit ec96690de8
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GPG Key ID: 24D68B725D5487D0
2 changed files with 15 additions and 0 deletions
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8
sound/soc/codecs/tlv320aic32x4.c
View File

@ -1013,6 +1013,14 @@ static int aic32x4_component_probe(struct snd_soc_component *component)
AIC32X4_LADC_EN | AIC32X4_RADC_EN); AIC32X4_LADC_EN | AIC32X4_RADC_EN);
snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg); snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
/*
* Enable the fast charging feature and ensure the needed 40ms ellapsed
* before using the analog circuits.
*/
snd_soc_component_write(component, AIC32X4_REFPOWERUP,
AIC32X4_REFPOWERUP_40MS);
msleep(40);
return 0; return 0;
} }

7
sound/soc/codecs/tlv320aic32x4.h
View File

@ -96,6 +96,7 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
#define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58) #define AIC32X4_FLOATINGINPUT AIC32X4_REG(1, 58)
#define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59) #define AIC32X4_LMICPGAVOL AIC32X4_REG(1, 59)
#define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60) #define AIC32X4_RMICPGAVOL AIC32X4_REG(1, 60)
#define AIC32X4_REFPOWERUP AIC32X4_REG(1, 123)
/* Bits, masks, and shifts */ /* Bits, masks, and shifts */
@ -205,6 +206,12 @@ int aic32x4_register_clocks(struct device *dev, const char *mclk_name);
#define AIC32X4_RMICPGANIN_IN1L_10K 0x10 #define AIC32X4_RMICPGANIN_IN1L_10K 0x10
#define AIC32X4_RMICPGANIN_CM1R_10K 0x40 #define AIC32X4_RMICPGANIN_CM1R_10K 0x40
/* AIC32X4_REFPOWERUP */
#define AIC32X4_REFPOWERUP_SLOW 0x04
#define AIC32X4_REFPOWERUP_40MS 0x05
#define AIC32X4_REFPOWERUP_80MS 0x06
#define AIC32X4_REFPOWERUP_120MS 0x07
/* Common mask and enable for all of the dividers */ /* Common mask and enable for all of the dividers */
#define AIC32X4_DIVEN BIT(7) #define AIC32X4_DIVEN BIT(7)
#define AIC32X4_DIV_MASK GENMASK(6, 0) #define AIC32X4_DIV_MASK GENMASK(6, 0)