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[MTD] [NAND] fsl_elbc_nand: implement support for flash-based BBT
This patch implements support for flash-based BBT for chips working through ELBC NAND controller, so that NAND core will not have to re-scan for bad blocks on every boot. Because ELBC controller may provide HW-generated ECCs we should adjust bbt pattern and bbt version positions in the OOB free area. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -130,6 +130,34 @@ static struct nand_bbt_descr largepage_memorybased = {
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.pattern = scan_ff_pattern,
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};
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/*
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* ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
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* interfere with ECC positions, that's why we implement our own descriptors.
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* OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
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*/
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static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
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static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
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static struct nand_bbt_descr bbt_main_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = bbt_pattern,
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};
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static struct nand_bbt_descr bbt_mirror_descr = {
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.options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
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NAND_BBT_2BIT | NAND_BBT_VERSION,
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.offs = 11,
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.len = 4,
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.veroffs = 15,
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.maxblocks = 4,
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.pattern = mirror_pattern,
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};
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/*=================================*/
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/*
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@ -767,8 +795,12 @@ static int fsl_elbc_chip_init(struct fsl_elbc_mtd *priv)
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chip->cmdfunc = fsl_elbc_cmdfunc;
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chip->waitfunc = fsl_elbc_wait;
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chip->bbt_td = &bbt_main_descr;
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chip->bbt_md = &bbt_mirror_descr;
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/* set up nand options */
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chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR;
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chip->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
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NAND_USE_FLASH_BBT;
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chip->controller = &ctrl->controller;
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chip->priv = priv;
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