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RealView: Use only the shadow mapping of ARM11MPCore local timers
All the cases where the local timer for a CPU is accessed happen on the corresponding current CPU, hence no need to access the per-CPU local timer mappings. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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4c3ea37171
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@ -114,7 +114,7 @@ extern void local_timer_interrupt(void);
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/*
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* Stop a local timer interrupt.
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*/
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extern void local_timer_stop(unsigned int cpu);
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extern void local_timer_stop(void);
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/*
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* Platform provides this to acknowledge a local timer IRQ
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@ -123,7 +123,7 @@ extern int local_timer_ack(void);
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#else
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static inline void local_timer_stop(unsigned int cpu)
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static inline void local_timer_stop(void)
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{
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}
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@ -132,7 +132,7 @@ static inline void local_timer_stop(unsigned int cpu)
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/*
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* Setup a local timer interrupt for a CPU.
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*/
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extern void local_timer_setup(unsigned int cpu);
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extern void local_timer_setup(void);
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/*
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* show local interrupt info
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@ -181,7 +181,7 @@ int __cpuexit __cpu_disable(void)
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/*
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* Stop the local timer for this CPU.
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*/
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local_timer_stop(cpu);
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local_timer_stop();
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/*
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* Flush user cache and TLB mappings, and then remove this CPU
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@ -284,7 +284,7 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
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/*
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* Setup local timer for this CPU.
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*/
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local_timer_setup(cpu);
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local_timer_setup();
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calibrate_delay();
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@ -629,7 +629,7 @@ void __init realview_timer_init(unsigned int timer_irq)
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* The dummy clock device has to be registered before the main device
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* so that the latter will broadcast the clock events
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*/
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local_timer_setup(smp_processor_id());
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local_timer_setup();
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#endif
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/*
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@ -52,8 +52,7 @@ extern struct clk realview_clcd_clk;
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extern struct clcd_board clcd_plat_data;
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extern void __iomem *gic_cpu_base_addr;
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#ifdef CONFIG_LOCAL_TIMERS
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extern void __iomem *twd_base_addr;
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extern unsigned int twd_size;
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extern void __iomem *twd_base;
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#endif
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extern void __iomem *timer0_va_base;
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extern void __iomem *timer1_va_base;
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@ -49,16 +49,14 @@
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#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
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#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x10100700
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#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
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#define REALVIEW_EB11MP_TWD_BASE 0x10100600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#else
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#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
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#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
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#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
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#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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@ -77,8 +77,7 @@
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*/
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#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
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#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
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#define REALVIEW_TC11MP_TWD_BASE 0x1F000700
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#define REALVIEW_TC11MP_TWD_SIZE 0x00000100
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#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
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#define REALVIEW_TC11MP_GIC_DIST_BASE 0x1F001000 /* Test chip interrupt controller distributor */
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#define REALVIEW_TC11MP_L220_BASE 0x1F002000 /* L220 registers */
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@ -38,18 +38,14 @@ void local_timer_interrupt(void)
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#ifdef CONFIG_LOCAL_TIMERS
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#define TWD_BASE(cpu) (twd_base_addr + (cpu) * twd_size)
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/* set up by the platform code */
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void __iomem *twd_base_addr;
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unsigned int twd_size;
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void __iomem *twd_base;
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static unsigned long mpcore_timer_rate;
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static void local_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *clk)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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unsigned long ctrl;
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switch(mode) {
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@ -68,17 +64,16 @@ static void local_timer_set_mode(enum clock_event_mode mode,
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ctrl = 0;
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}
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__raw_writel(ctrl, base + TWD_TIMER_CONTROL);
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__raw_writel(ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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static int local_timer_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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unsigned long ctrl = __raw_readl(base + TWD_TIMER_CONTROL);
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unsigned long ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
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__raw_writel(evt, base + TWD_TIMER_COUNTER);
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__raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, base + TWD_TIMER_CONTROL);
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__raw_writel(evt, twd_base + TWD_TIMER_COUNTER);
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__raw_writel(ctrl | TWD_TIMER_CONTROL_ENABLE, twd_base + TWD_TIMER_CONTROL);
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return 0;
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}
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@ -91,19 +86,16 @@ static int local_timer_set_next_event(unsigned long evt,
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*/
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int local_timer_ack(void)
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{
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void __iomem *base = TWD_BASE(smp_processor_id());
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if (__raw_readl(base + TWD_TIMER_INTSTAT)) {
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__raw_writel(1, base + TWD_TIMER_INTSTAT);
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if (__raw_readl(twd_base + TWD_TIMER_INTSTAT)) {
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__raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
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return 1;
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}
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return 0;
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}
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static void __cpuinit twd_calibrate_rate(unsigned int cpu)
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static void __cpuinit twd_calibrate_rate(void)
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{
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void __iomem *base = TWD_BASE(cpu);
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unsigned long load, count;
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u64 waitjiffies;
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@ -124,15 +116,15 @@ static void __cpuinit twd_calibrate_rate(unsigned int cpu)
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waitjiffies += 5;
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/* enable, no interrupt or reload */
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__raw_writel(0x1, base + TWD_TIMER_CONTROL);
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__raw_writel(0x1, twd_base + TWD_TIMER_CONTROL);
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/* maximum value */
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__raw_writel(0xFFFFFFFFU, base + TWD_TIMER_COUNTER);
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__raw_writel(0xFFFFFFFFU, twd_base + TWD_TIMER_COUNTER);
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while (get_jiffies_64() < waitjiffies)
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udelay(10);
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count = __raw_readl(base + TWD_TIMER_COUNTER);
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count = __raw_readl(twd_base + TWD_TIMER_COUNTER);
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mpcore_timer_rate = (0xFFFFFFFFU - count) * (HZ / 5);
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@ -142,18 +134,19 @@ static void __cpuinit twd_calibrate_rate(unsigned int cpu)
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load = mpcore_timer_rate / HZ;
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__raw_writel(load, base + TWD_TIMER_LOAD);
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__raw_writel(load, twd_base + TWD_TIMER_LOAD);
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}
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/*
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* Setup the local clock events for a CPU.
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*/
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void __cpuinit local_timer_setup(unsigned int cpu)
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void __cpuinit local_timer_setup(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
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unsigned long flags;
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twd_calibrate_rate(cpu);
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twd_calibrate_rate();
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clk->name = "local_timer";
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clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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@ -178,9 +171,9 @@ void __cpuinit local_timer_setup(unsigned int cpu)
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/*
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* take a local timer down
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*/
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void __cpuexit local_timer_stop(unsigned int cpu)
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void __cpuexit local_timer_stop(void)
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{
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__raw_writel(0, TWD_BASE(cpu) + TWD_TIMER_CONTROL);
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__raw_writel(0, twd_base + TWD_TIMER_CONTROL);
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}
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#else /* CONFIG_LOCAL_TIMERS */
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@ -190,8 +183,9 @@ static void dummy_timer_set_mode(enum clock_event_mode mode,
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{
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}
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void __cpuinit local_timer_setup(unsigned int cpu)
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void __cpuinit local_timer_setup(void)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
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clk->name = "dummy_timer";
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@ -238,7 +238,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
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if ((machine_is_realview_eb() &&
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(core_tile_eb11mp() || core_tile_a9mp())) ||
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machine_is_realview_pb11mp())
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local_timer_setup(cpu);
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local_timer_setup();
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#endif
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/*
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@ -344,8 +344,7 @@ static void __init realview_eb_timer_init(void)
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if (core_tile_eb11mp() || core_tile_a9mp()) {
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base_addr = __io_address(REALVIEW_EB11MP_TWD_BASE);
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twd_size = REALVIEW_EB11MP_TWD_SIZE;
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twd_base = __io_address(REALVIEW_EB11MP_TWD_BASE);
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#endif
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timer_irq = IRQ_EB11MP_TIMER0_1;
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} else
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@ -292,8 +292,7 @@ static void __init realview_pb11mp_timer_init(void)
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timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
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#ifdef CONFIG_LOCAL_TIMERS
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twd_base_addr = __io_address(REALVIEW_TC11MP_TWD_BASE);
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twd_size = REALVIEW_TC11MP_TWD_SIZE;
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twd_base = __io_address(REALVIEW_TC11MP_TWD_BASE);
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#endif
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realview_timer_init(IRQ_TC11MP_TIMER0_1);
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}
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