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drm/amdkfd: Let VRAM allocations go to GTT domain on small APUs
Small APUs(i.e., consumer, embedded products) usually have a small carveout device memory which can't satisfy most compute workloads memory allocation requirements. We can't even run a Basic MNIST Example with a default 512MB carveout. https://github.com/pytorch/examples/tree/main/mnist. Error Log: "torch.cuda.OutOfMemoryError: HIP out of memory. Tried to allocate 84.00 MiB. GPU 0 has a total capacity of 512.00 MiB of which 0 bytes is free. Of the allocated memory 103.83 MiB is allocated by PyTorch, and 22.17 MiB is reserved by PyTorch but unallocated" Though we can change BIOS settings to enlarge carveout size, which is inflexible and may bring complaint. On the other hand, the memory resource can't be effectively used between host and device. The solution is MI300A approach, i.e., let VRAM allocations go to GTT. Then device and host can flexibly and effectively share memory resource. v2: Report local_mem_size_private as 0. (Felix) Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -455,6 +455,9 @@ void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
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else
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mem_info->local_mem_size_private =
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KFD_XCP_MEMORY_SIZE(adev, xcp->id);
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} else if (adev->flags & AMD_IS_APU) {
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mem_info->local_mem_size_public = (ttm_tt_pages_limit() << PAGE_SHIFT);
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mem_info->local_mem_size_private = 0;
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} else {
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mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
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mem_info->local_mem_size_private = adev->gmc.real_vram_size -
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@ -824,6 +827,8 @@ u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
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}
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do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
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return ALIGN_DOWN(tmp, PAGE_SIZE);
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} else if (adev->flags & AMD_IS_APU) {
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return (ttm_tt_pages_limit() << PAGE_SHIFT);
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} else {
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return adev->gmc.real_vram_size;
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}
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@ -196,7 +196,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
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return -EINVAL;
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vram_size = KFD_XCP_MEMORY_SIZE(adev, xcp_id);
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if (adev->gmc.is_app_apu) {
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if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
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system_mem_needed = size;
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ttm_mem_needed = size;
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}
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@ -232,7 +232,8 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
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"adev reference can't be null when vram is used");
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if (adev && xcp_id >= 0) {
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adev->kfd.vram_used[xcp_id] += vram_needed;
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adev->kfd.vram_used_aligned[xcp_id] += adev->gmc.is_app_apu ?
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adev->kfd.vram_used_aligned[xcp_id] +=
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(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) ?
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vram_needed :
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ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN);
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}
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@ -260,7 +261,7 @@ void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
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if (adev) {
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adev->kfd.vram_used[xcp_id] -= size;
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if (adev->gmc.is_app_apu) {
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if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
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adev->kfd.vram_used_aligned[xcp_id] -= size;
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kfd_mem_limit.system_mem_used -= size;
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kfd_mem_limit.ttm_mem_used -= size;
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@ -889,7 +890,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem,
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* if peer device has large BAR. In contrast, access over xGMI is
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* allowed for both small and large BAR configurations of peer device
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*/
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if ((adev != bo_adev && !adev->gmc.is_app_apu) &&
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if ((adev != bo_adev && !(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU)) &&
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((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) ||
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(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) ||
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(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) {
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@ -1657,7 +1658,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
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- atomic64_read(&adev->vram_pin_size)
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- reserved_for_pt;
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if (adev->gmc.is_app_apu) {
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if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
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system_mem_available = no_system_mem_limit ?
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kfd_mem_limit.max_system_mem_limit :
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kfd_mem_limit.max_system_mem_limit -
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@ -1705,7 +1706,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
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if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
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domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM;
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if (adev->gmc.is_app_apu) {
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if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) {
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domain = AMDGPU_GEM_DOMAIN_GTT;
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alloc_domain = AMDGPU_GEM_DOMAIN_GTT;
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alloc_flags = 0;
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@ -1952,7 +1953,7 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
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if (size) {
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if (!is_imported &&
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(mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM ||
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(adev->gmc.is_app_apu &&
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((adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) &&
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mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_GTT)))
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*size = bo_size;
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else
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@ -2374,8 +2375,9 @@ static int import_obj_create(struct amdgpu_device *adev,
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(*mem)->dmabuf = dma_buf;
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(*mem)->bo = bo;
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(*mem)->va = va;
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(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !adev->gmc.is_app_apu ?
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AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
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(*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) &&
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!(adev->gmc.is_app_apu || adev->flags & AMD_IS_APU) ?
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AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT;
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(*mem)->mapped_to_gpu_memory = 0;
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(*mem)->process_info = avm->process_info;
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@ -1023,7 +1023,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
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if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 1))
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return -EINVAL;
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if (adev->gmc.is_app_apu)
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if (adev->gmc.is_app_apu || adev->flags & AMD_IS_APU)
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return 0;
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pgmap = &kfddev->pgmap;
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@ -2619,7 +2619,8 @@ svm_range_best_restore_location(struct svm_range *prange,
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return -1;
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}
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if (node->adev->gmc.is_app_apu)
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if (node->adev->gmc.is_app_apu ||
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node->adev->flags & AMD_IS_APU)
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return 0;
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if (prange->preferred_loc == gpuid ||
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@ -3337,7 +3338,8 @@ svm_range_best_prefetch_location(struct svm_range *prange)
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goto out;
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}
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if (bo_node->adev->gmc.is_app_apu) {
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if (bo_node->adev->gmc.is_app_apu ||
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bo_node->adev->flags & AMD_IS_APU) {
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best_loc = 0;
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goto out;
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}
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@ -201,7 +201,8 @@ void svm_range_list_lock_and_flush_work(struct svm_range_list *svms, struct mm_s
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* is initialized to not 0 when page migration register device memory.
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*/
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#define KFD_IS_SVM_API_SUPPORTED(adev) ((adev)->kfd.pgmap.type != 0 ||\
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(adev)->gmc.is_app_apu)
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(adev)->gmc.is_app_apu ||\
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((adev)->flags & AMD_IS_APU))
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void svm_range_bo_unref_async(struct svm_range_bo *svm_bo);
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