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RDMA/qedr: Add EDPM max size to alloc ucontext response
User space should receive the maximum edpm size from kernel driver,
similar to other edpm/ldpm related limits. Add an additional parameter to
the alloc_ucontext_resp structure for the edpm maximum size.
In addition, pass an indication from user-space to kernel
(and not just kernel to user) that the DPM sizes are supported.
This is for supporting backward-forward compatibility between driver and
lib for everything related to DPM transaction and limit sizes.
This should have been part of commit mentioned in Fixes tag.
Link: https://lore.kernel.org/r/20200707063100.3811-3-michal.kalderon@marvell.com
Fixes: 93a3d05f9d
("RDMA/qedr: Add kernel capability flags for dpm enabled mode")
Signed-off-by: Ariel Elior <ariel.elior@marvell.com>
Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
parent
bbe4f42452
commit
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@ -320,9 +320,12 @@ int qedr_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata)
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QEDR_DPM_TYPE_ROCE_LEGACY |
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QEDR_DPM_TYPE_ROCE_EDPM_MODE;
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uresp.dpm_flags |= QEDR_DPM_SIZES_SET;
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uresp.ldpm_limit_size = QEDR_LDPM_MAX_SIZE;
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uresp.edpm_trans_size = QEDR_EDPM_TRANS_SIZE;
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if (ureq.context_flags & QEDR_SUPPORT_DPM_SIZES) {
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uresp.dpm_flags |= QEDR_DPM_SIZES_SET;
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uresp.ldpm_limit_size = QEDR_LDPM_MAX_SIZE;
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uresp.edpm_trans_size = QEDR_EDPM_TRANS_SIZE;
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uresp.edpm_limit_size = QEDR_EDPM_MAX_SIZE;
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}
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uresp.wids_enabled = 1;
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uresp.wid_count = oparams.wid_count;
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@ -40,7 +40,8 @@
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/* user kernel communication data structures. */
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enum qedr_alloc_ucontext_flags {
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QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0,
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QEDR_ALLOC_UCTX_DB_REC = 1 << 1
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QEDR_ALLOC_UCTX_DB_REC = 1 << 1,
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QEDR_SUPPORT_DPM_SIZES = 1 << 2,
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};
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struct qedr_alloc_ucontext_req {
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@ -50,6 +51,7 @@ struct qedr_alloc_ucontext_req {
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#define QEDR_LDPM_MAX_SIZE (8192)
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#define QEDR_EDPM_TRANS_SIZE (64)
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#define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE)
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enum qedr_rdma_dpm_type {
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QEDR_DPM_TYPE_NONE = 0,
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@ -77,6 +79,8 @@ struct qedr_alloc_ucontext_resp {
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__u16 ldpm_limit_size;
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__u8 edpm_trans_size;
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__u8 reserved;
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__u16 edpm_limit_size;
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__u8 padding[6];
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};
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struct qedr_alloc_pd_ureq {
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